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1; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 < %s | FileCheck %s2target datalayout = "e-p:32:32:32-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f16:16:16-f32:32:32-f64:32:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"3 4 5; We can vectorize this code because if the address computation would wrap then6; a load from 0 would take place which is undefined behaviour in address space 07; according to LLVM IR semantics.8 9; PR1659210 11; CHECK-LABEL: @safe(12; CHECK: <4 x float>13 14define void @safe(ptr %A, ptr %B, float %K) {15entry:16 br label %"<bb 3>"17 18"<bb 3>":19 %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]20 %pp3 = getelementptr float, ptr %A, i32 %i_1521 %D.1396_10 = load float, ptr %pp3, align 422 %pp24 = getelementptr float, ptr %B, i32 %i_1523 %D.1398_15 = load float, ptr %pp24, align 424 %D.1399_17 = fadd float %D.1398_15, %K25 %D.1400_18 = fmul float %D.1396_10, %D.1399_1726 store float %D.1400_18, ptr %pp3, align 427 %i_19 = add nsw i32 %i_15, 128 %exitcond = icmp ne i32 %i_19, 6429 br i1 %exitcond, label %"<bb 3>", label %return30 31return:32 ret void33}34 35; In a non-default address space we don't have this rule.36 37; CHECK-LABEL: @notsafe(38; CHECK-NOT: <4 x float>39 40define void @notsafe(ptr addrspace(5) %A, ptr %B, float %K) {41entry:42 br label %"<bb 3>"43 44"<bb 3>":45 %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]46 %pp3 = getelementptr float, ptr addrspace(5) %A, i32 %i_1547 %D.1396_10 = load float, ptr addrspace(5) %pp3, align 448 %pp24 = getelementptr float, ptr %B, i32 %i_1549 %D.1398_15 = load float, ptr %pp24, align 450 %D.1399_17 = fadd float %D.1398_15, %K51 %D.1400_18 = fmul float %D.1396_10, %D.1399_1752 store float %D.1400_18, ptr addrspace(5) %pp3, align 453 %i_19 = add nsw i32 %i_15, 154 %exitcond = icmp ne i32 %i_19, 6455 br i1 %exitcond, label %"<bb 3>", label %return56 57return:58 ret void59}60 61 62