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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -scalable-vectorization=on -force-target-supports-scalable-vectors=true -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck %s3 4define i32 @iv_live_out_wide(ptr %dst) {5; CHECK-LABEL: define i32 @iv_live_out_wide(6; CHECK-SAME: ptr [[DST:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[STEP_1:%.*]] = sext i8 0 to i329; CHECK-NEXT: [[STEP_2:%.*]] = add nsw i32 [[STEP_1]], 110; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()11; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 [[TMP0]], 212; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 2000, [[TMP1]]13; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]14; CHECK: [[VECTOR_PH]]:15; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vscale.i32()16; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP4]], 217; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[TMP5]], i64 018; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer19; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 220; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 2000, [[TMP6]]21; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 2000, [[N_MOD_VF]]22; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[STEP_2]], i64 023; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer24; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32()25; CHECK-NEXT: [[TMP8:%.*]] = mul <vscale x 2 x i32> [[TMP7]], splat (i32 1)26; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i32> zeroinitializer, [[TMP8]]27; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]28; CHECK: [[VECTOR_BODY]]:29; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]30; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]31; CHECK-NEXT: [[STEP_ADD:%.*]] = add <vscale x 2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]32; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[INDEX]]33; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()34; CHECK-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP12]], 135; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[TMP13]]36; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP10]], align 237; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP14]], align 238; CHECK-NEXT: [[TMP15:%.*]] = add <vscale x 2 x i32> [[BROADCAST_SPLAT]], [[STEP_ADD]]39; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP6]]40; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i32> [[STEP_ADD]], [[BROADCAST_SPLAT2]]41; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]42; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]43; CHECK: [[MIDDLE_BLOCK]]:44; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32()45; CHECK-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 246; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP18]], 147; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 2 x i32> [[TMP15]], i32 [[TMP19]]48; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 2000, [[N_VEC]]49; CHECK-NEXT: br i1 [[CMP_N]], label %[[E_EXIT:.*]], label %[[SCALAR_PH]]50; CHECK: [[SCALAR_PH]]:51; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]52; CHECK-NEXT: br label %[[LOOP:.*]]53; CHECK: [[LOOP]]:54; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]55; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[IV]]56; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 257; CHECK-NEXT: [[IV_NEXT]] = add i32 [[STEP_2]], [[IV]]58; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[IV_NEXT]], 200059; CHECK-NEXT: br i1 [[CMP_I]], label %[[LOOP]], label %[[E_EXIT]], !llvm.loop [[LOOP3:![0-9]+]]60; CHECK: [[E_EXIT]]:61; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ]62; CHECK-NEXT: ret i32 [[RES]]63;64entry:65 %step.1 = sext i8 0 to i3266 %step.2 = add nsw i32 %step.1, 167 br label %loop68 69loop:70 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]71 %gep.dst = getelementptr inbounds i16, ptr %dst, i32 %iv72 store i16 0, ptr %gep.dst, align 273 %iv.next = add i32 %step.2, %iv74 %cmp.i = icmp slt i32 %iv.next, 200075 br i1 %cmp.i, label %loop, label %e.exit76 77e.exit:78 %res = phi i32 [ %iv.next, %loop ]79 ret i32 %res80}81;.82; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}83; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}84; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}85; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}86;.87