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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4; Test cases for selecting the index with the minimum value.5 6define i64 @test_vectorize_select_umin_idx(ptr %src, i64 %n) {7; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx(8; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 411; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]12; CHECK: [[VECTOR_PH]]:13; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 414; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]15; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]16; CHECK: [[VECTOR_BODY]]:17; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]18; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]19; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]20; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 140), %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]21; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV1]]22; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[GEP1]], align 423; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD]]24; CHECK-NEXT: [[TMP3]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD]])25; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP2]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]]26; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV1]], 427; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)28; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]29; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]30; CHECK: [[MIDDLE_BLOCK]]:31; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP3]])32; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 033; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer34; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP3]], [[BROADCAST_SPLAT]]35; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -9223372036854775808)36; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP8]])37; CHECK-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP9]], -922337203685477580838; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP9]], i64 039; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]40; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]41; CHECK: [[SCALAR_PH]]:42; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]43; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]44; CHECK-NEXT: [[BC_MERGE_RDX2:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 140, %[[ENTRY]] ]45; CHECK-NEXT: br label %[[LOOP:.*]]46; CHECK: [[LOOP]]:47; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]48; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]49; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ [[BC_MERGE_RDX2]], %[[SCALAR_PH]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]50; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]51; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 452; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]53; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])54; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]55; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 156; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]57; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]58; CHECK: [[EXIT]]:59; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]60; CHECK-NEXT: ret i64 [[RES]]61;62entry:63 br label %loop64 65loop:66 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]67 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]68 %min.val = phi i64 [ 140, %entry ], [ %min.val.next, %loop ]69 %gep = getelementptr i64, ptr %src, i64 %iv70 %l = load i64, ptr %gep71 %cmp = icmp uge i64 %min.val, %l72 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)73 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx74 %iv.next = add nuw nsw i64 %iv, 175 %exitcond.not = icmp eq i64 %iv.next, %n76 br i1 %exitcond.not, label %exit, label %loop77 78exit:79 %res = phi i64 [ %min.idx.next, %loop ]80 ret i64 %res81}82 83define i64 @test_vectorize_select_umin_idx_cond_flipped(ptr %src, i64 %n) {84; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx_cond_flipped(85; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {86; CHECK-NEXT: [[ENTRY:.*]]:87; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 488; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]89; CHECK: [[VECTOR_PH]]:90; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 491; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]92; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]93; CHECK: [[VECTOR_BODY]]:94; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]95; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]96; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]97; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 130), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]98; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV1]]99; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[GEP1]], align 4100; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], [[VEC_PHI1]]101; CHECK-NEXT: [[TMP2]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD]])102; CHECK-NEXT: [[TMP3]] = select <4 x i1> [[TMP1]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]]103; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV1]], 4104; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)105; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]106; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]107; CHECK: [[MIDDLE_BLOCK]]:108; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP2]])109; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP5]], i64 0110; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer111; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT]]112; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP3]], <4 x i64> splat (i64 -9223372036854775808)113; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP7]])114; CHECK-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808115; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 0116; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]117; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]118; CHECK: [[SCALAR_PH]]:119; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]120; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]121; CHECK-NEXT: [[BC_MERGE_RDX2:%.*]] = phi i64 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 130, %[[ENTRY]] ]122; CHECK-NEXT: br label %[[LOOP:.*]]123; CHECK: [[LOOP]]:124; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]125; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]126; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ [[BC_MERGE_RDX2]], %[[SCALAR_PH]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]127; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]128; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4129; CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[L]], [[MIN_VAL]]130; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])131; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]132; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1133; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]134; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]135; CHECK: [[EXIT]]:136; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]137; CHECK-NEXT: ret i64 [[RES]]138;139entry:140 br label %loop141 142loop:143 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]144 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]145 %min.val = phi i64 [ 130, %entry ], [ %min.val.next, %loop ]146 %gep = getelementptr i64, ptr %src, i64 %iv147 %l = load i64, ptr %gep148 %cmp = icmp ule i64 %l, %min.val149 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)150 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx151 %iv.next = add nuw nsw i64 %iv, 1152 %exitcond.not = icmp eq i64 %iv.next, %n153 br i1 %exitcond.not, label %exit, label %loop154 155exit:156 %res = phi i64 [ %min.idx.next, %loop ]157 ret i64 %res158}159 160define i64 @test_vectorize_select_umin_idx_select_ops_flipped(ptr %src, i64 %n) {161; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx_select_ops_flipped(162; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {163; CHECK-NEXT: [[ENTRY:.*]]:164; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4165; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]166; CHECK: [[VECTOR_PH]]:167; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4168; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]169; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]170; CHECK: [[VECTOR_BODY]]:171; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]172; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]173; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]174; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 120), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]175; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV1]]176; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[GEP1]], align 4177; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i64> [[WIDE_LOAD]], [[VEC_PHI1]]178; CHECK-NEXT: [[TMP2]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD]])179; CHECK-NEXT: [[TMP3]] = select <4 x i1> [[TMP1]], <4 x i64> [[VEC_PHI]], <4 x i64> [[VEC_IND]]180; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV1]], 4181; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)182; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]183; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]184; CHECK: [[MIDDLE_BLOCK]]:185; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP2]])186; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP5]], i64 0187; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer188; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT]]189; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP3]], <4 x i64> splat (i64 -9223372036854775808)190; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP7]])191; CHECK-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808192; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 0193; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]194; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]195; CHECK: [[SCALAR_PH]]:196; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]197; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]198; CHECK-NEXT: [[BC_MERGE_RDX2:%.*]] = phi i64 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 120, %[[ENTRY]] ]199; CHECK-NEXT: br label %[[LOOP:.*]]200; CHECK: [[LOOP]]:201; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]202; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]203; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ [[BC_MERGE_RDX2]], %[[SCALAR_PH]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]204; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]205; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4206; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[L]], [[MIN_VAL]]207; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])208; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[MIN_IDX]], i64 [[IV]]209; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1210; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]211; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]212; CHECK: [[EXIT]]:213; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]214; CHECK-NEXT: ret i64 [[RES]]215;216entry:217 br label %loop218 219loop:220 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]221 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]222 %min.val = phi i64 [ 120, %entry ], [ %min.val.next, %loop ]223 %gep = getelementptr i64, ptr %src, i64 %iv224 %l = load i64, ptr %gep225 %cmp = icmp ugt i64 %l, %min.val226 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)227 %min.idx.next = select i1 %cmp, i64 %min.idx, i64 %iv228 %iv.next = add nuw nsw i64 %iv, 1229 %exitcond.not = icmp eq i64 %iv.next, %n230 br i1 %exitcond.not, label %exit, label %loop231 232exit:233 %res = phi i64 [ %min.idx.next, %loop ]234 ret i64 %res235}236 237define i64 @test_vectorize_select_umin_via_select_idx(ptr %src, i64 %n) {238; CHECK-LABEL: define i64 @test_vectorize_select_umin_via_select_idx(239; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {240; CHECK-NEXT: [[ENTRY:.*]]:241; CHECK-NEXT: br label %[[LOOP:.*]]242; CHECK: [[LOOP]]:243; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]244; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]245; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 110, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]246; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]247; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4248; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]249; CHECK-NEXT: [[MIN_VAL_NEXT]] = select i1 [[CMP]], i64 [[L]], i64 [[MIN_VAL]]250; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]251; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1252; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]253; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]254; CHECK: [[EXIT]]:255; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]256; CHECK-NEXT: ret i64 [[RES]]257;258entry:259 br label %loop260 261loop:262 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]263 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]264 %min.val = phi i64 [ 110, %entry ], [ %min.val.next, %loop ]265 %gep = getelementptr i64, ptr %src, i64 %iv266 %l = load i64, ptr %gep267 %cmp = icmp uge i64 %min.val, %l268 %min.val.next = select i1 %cmp, i64 %l, i64 %min.val269 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx270 %iv.next = add nuw nsw i64 %iv, 1271 %exitcond.not = icmp eq i64 %iv.next, %n272 br i1 %exitcond.not, label %exit, label %loop273 274exit:275 %res = phi i64 [ %min.idx.next, %loop ]276 ret i64 %res277}278 279define i64 @test_vectorize_select_umin_idx_all_exit_inst(ptr %src, ptr %umin, i64 %n) {280; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx_all_exit_inst(281; CHECK-SAME: ptr [[SRC:%.*]], ptr [[UMIN:%.*]], i64 [[N:%.*]]) {282; CHECK-NEXT: [[ENTRY:.*]]:283; CHECK-NEXT: br label %[[LOOP:.*]]284; CHECK: [[LOOP]]:285; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]286; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]287; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 100, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]288; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]289; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4290; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]291; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])292; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]293; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1294; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]295; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]296; CHECK: [[EXIT]]:297; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]298; CHECK-NEXT: [[RES_UMIN:%.*]] = phi i64 [ [[MIN_VAL_NEXT]], %[[LOOP]] ]299; CHECK-NEXT: store i64 [[RES_UMIN]], ptr [[UMIN]], align 4300; CHECK-NEXT: ret i64 [[RES]]301;302entry:303 br label %loop304 305loop:306 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]307 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]308 %min.val = phi i64 [ 100, %entry ], [ %min.val.next, %loop ]309 %gep = getelementptr i64, ptr %src, i64 %iv310 %l = load i64, ptr %gep311 %cmp = icmp uge i64 %min.val, %l312 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)313 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx314 %iv.next = add nuw nsw i64 %iv, 1315 %exitcond.not = icmp eq i64 %iv.next, %n316 br i1 %exitcond.not, label %exit, label %loop317 318exit:319 %res = phi i64 [ %min.idx.next, %loop ]320 %res.umin = phi i64 [ %min.val.next, %loop ]321 store i64 %res.umin, ptr %umin322 ret i64 %res323}324 325define i64 @test_vectorize_select_umin_idx_min_ops_switched(ptr %src, i64 %n) {326; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx_min_ops_switched(327; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {328; CHECK-NEXT: [[ENTRY:.*]]:329; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4330; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]331; CHECK: [[VECTOR_PH]]:332; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4333; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]334; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]335; CHECK: [[VECTOR_BODY]]:336; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]337; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]338; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]339; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 90), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]340; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]341; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[GEP]], align 4342; CHECK-NEXT: [[TMP1:%.*]] = icmp uge <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD]]343; CHECK-NEXT: [[TMP2]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[WIDE_LOAD]], <4 x i64> [[VEC_PHI1]])344; CHECK-NEXT: [[TMP3]] = select <4 x i1> [[TMP1]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]]345; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4346; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)347; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]348; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]349; CHECK: [[MIDDLE_BLOCK]]:350; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP2]])351; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP5]], i64 0352; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer353; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT]]354; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP3]], <4 x i64> splat (i64 -9223372036854775808)355; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP7]])356; CHECK-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808357; CHECK-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 0358; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]359; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]360; CHECK: [[SCALAR_PH]]:361; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]362; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]363; CHECK-NEXT: [[BC_MERGE_RDX2:%.*]] = phi i64 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 90, %[[ENTRY]] ]364; CHECK-NEXT: br label %[[LOOP:.*]]365; CHECK: [[LOOP]]:366; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]367; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]368; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ [[BC_MERGE_RDX2]], %[[SCALAR_PH]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]369; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV1]]370; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP1]], align 4371; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]372; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[L]], i64 [[MIN_VAL]])373; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV1]], i64 [[MIN_IDX]]374; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1375; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]376; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]377; CHECK: [[EXIT]]:378; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]379; CHECK-NEXT: ret i64 [[RES]]380;381entry:382 br label %loop383 384loop:385 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]386 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]387 %min.val = phi i64 [ 90, %entry ], [ %min.val.next, %loop ]388 %gep = getelementptr i64, ptr %src, i64 %iv389 %l = load i64, ptr %gep390 %cmp = icmp uge i64 %min.val, %l391 %min.val.next = tail call i64 @llvm.umin.i64(i64 %l, i64 %min.val)392 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx393 %iv.next = add nuw nsw i64 %iv, 1394 %exitcond.not = icmp eq i64 %iv.next, %n395 br i1 %exitcond.not, label %exit, label %loop396 397exit:398 %res = phi i64 [ %min.idx.next, %loop ]399 ret i64 %res400}401 402define i64 @test_not_vectorize_select_no_min_reduction(ptr %src, i64 %n) {403; CHECK-LABEL: define i64 @test_not_vectorize_select_no_min_reduction(404; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {405; CHECK-NEXT: [[ENTRY:.*]]:406; CHECK-NEXT: br label %[[LOOP:.*]]407; CHECK: [[LOOP]]:408; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]409; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]410; CHECK-NEXT: [[RED_VAL:%.*]] = phi i64 [ 80, %[[ENTRY]] ], [ [[RED_VAL_NEXT:%.*]], %[[LOOP]] ]411; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]412; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4413; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[RED_VAL]], [[L]]414; CHECK-NEXT: [[RED_VAL_NEXT]] = add i64 [[RED_VAL]], [[L]]415; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]416; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1417; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]418; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]419; CHECK: [[EXIT]]:420; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]421; CHECK-NEXT: ret i64 [[RES]]422;423entry:424 br label %loop425 426loop:427 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]428 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]429 %red.val = phi i64 [ 80, %entry ], [ %red.val.next, %loop ]430 %gep = getelementptr i64, ptr %src, i64 %iv431 %l = load i64, ptr %gep432 %cmp = icmp uge i64 %red.val, %l433 %red.val.next = add i64 %red.val, %l434 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx435 %iv.next = add nuw nsw i64 %iv, 1436 %exitcond.not = icmp eq i64 %iv.next, %n437 br i1 %exitcond.not, label %exit, label %loop438 439exit:440 %res = phi i64 [ %min.idx.next, %loop ]441 ret i64 %res442}443 444define i64 @test_cmp_and_umin_use_different_values(ptr %src, i64 %x, i64 %n) {445; CHECK-LABEL: define i64 @test_cmp_and_umin_use_different_values(446; CHECK-SAME: ptr [[SRC:%.*]], i64 [[X:%.*]], i64 [[N:%.*]]) {447; CHECK-NEXT: [[ENTRY:.*]]:448; CHECK-NEXT: br label %[[LOOP:.*]]449; CHECK: [[LOOP]]:450; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]451; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]452; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 70, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]453; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]454; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4455; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[X]]456; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])457; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]458; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1459; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]460; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]461; CHECK: [[EXIT]]:462; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]463; CHECK-NEXT: ret i64 [[RES]]464;465entry:466 br label %loop467 468loop:469 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]470 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]471 %min.val = phi i64 [ 70, %entry ], [ %min.val.next, %loop ]472 %gep = getelementptr i64, ptr %src, i64 %iv473 %l = load i64, ptr %gep474 %cmp = icmp uge i64 %min.val, %x475 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)476 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx477 %iv.next = add nuw nsw i64 %iv, 1478 %exitcond.not = icmp eq i64 %iv.next, %n479 br i1 %exitcond.not, label %exit, label %loop480 481exit:482 %res = phi i64 [ %min.idx.next, %loop ]483 ret i64 %res484}485 486define i32 @test_vectorize_select_umin_idx_with_trunc(ptr %src, i64 %n) {487; CHECK-LABEL: define i32 @test_vectorize_select_umin_idx_with_trunc(488; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {489; CHECK-NEXT: [[ENTRY:.*]]:490; CHECK-NEXT: br label %[[LOOP:.*]]491; CHECK: [[LOOP]]:492; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]493; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]494; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 60, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]495; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]496; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4497; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]498; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])499; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[IV]] to i32500; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i32 [[TRUNC]], i32 [[MIN_IDX]]501; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1502; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]503; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]504; CHECK: [[EXIT]]:505; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]506; CHECK-NEXT: ret i32 [[RES]]507;508entry:509 br label %loop510 511loop:512 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]513 %min.idx = phi i32 [ 0, %entry ], [ %min.idx.next, %loop ]514 %min.val = phi i64 [ 60, %entry ], [ %min.val.next, %loop ]515 %gep = getelementptr i64, ptr %src, i64 %iv516 %l = load i64, ptr %gep517 %cmp = icmp uge i64 %min.val, %l518 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)519 %trunc = trunc i64 %iv to i32520 %min.idx.next = select i1 %cmp, i32 %trunc, i32 %min.idx521 %iv.next = add nuw nsw i64 %iv, 1522 %exitcond.not = icmp eq i64 %iv.next, %n523 br i1 %exitcond.not, label %exit, label %loop524 525exit:526 %res = phi i32 [ %min.idx.next, %loop ]527 ret i32 %res528}529 530define ptr @test_with_ptr_index(ptr %start, ptr %end) {531; CHECK-LABEL: define ptr @test_with_ptr_index(532; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {533; CHECK-NEXT: [[ENTRY:.*]]:534; CHECK-NEXT: br label %[[LOOP:.*]]535; CHECK: [[LOOP]]:536; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]537; CHECK-NEXT: [[MIN_IDX:%.*]] = phi ptr [ null, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]538; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 60, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]539; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[IV]], align 4540; CHECK-NEXT: [[CMP7_US:%.*]] = icmp ule i64 [[L]], [[MIN_VAL]]541; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])542; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP7_US]], ptr [[IV]], ptr [[MIN_IDX]]543; CHECK-NEXT: [[IV_NEXT]] = getelementptr i32, ptr [[IV]], i64 1544; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq ptr [[IV_NEXT]], [[END]]545; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]546; CHECK: [[EXIT]]:547; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[MIN_IDX_NEXT]], %[[LOOP]] ]548; CHECK-NEXT: ret ptr [[RES]]549;550entry:551 br label %loop552 553loop:554 %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ]555 %min.idx = phi ptr [ null, %entry ], [ %min.idx.next, %loop ]556 %min.val = phi i64 [ 60, %entry ], [ %min.val.next, %loop ]557 %l = load i64, ptr %iv558 %cmp7.us = icmp ule i64 %l, %min.val559 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)560 %min.idx.next = select i1 %cmp7.us, ptr %iv, ptr %min.idx561 %iv.next = getelementptr i32, ptr %iv, i64 1562 %exitcond.not = icmp eq ptr %iv.next, %end563 br i1 %exitcond.not, label %exit, label %loop564 565exit:566 %res = phi ptr [ %min.idx.next, %loop ]567 ret ptr %res568}569 570define i64 @test_no_vectorize_select_iv_decrement(ptr %src) {571; CHECK-LABEL: define i64 @test_no_vectorize_select_iv_decrement(572; CHECK-SAME: ptr [[SRC:%.*]]) {573; CHECK-NEXT: [[ENTRY:.*]]:574; CHECK-NEXT: br label %[[LOOP:.*]]575; CHECK: [[LOOP]]:576; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1000, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]577; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]578; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 50, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]579; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]580; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4581; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]582; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])583; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]584; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], -1585; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 0586; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]587; CHECK: [[EXIT]]:588; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]589; CHECK-NEXT: ret i64 [[RES]]590;591entry:592 br label %loop593 594loop:595 %iv = phi i64 [ 1000, %entry ], [ %iv.next, %loop ]596 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]597 %min.val = phi i64 [ 50, %entry ], [ %min.val.next, %loop ]598 %gep = getelementptr i64, ptr %src, i64 %iv599 %l = load i64, ptr %gep600 %cmp = icmp uge i64 %min.val, %l601 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)602 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx603 %iv.next = add nuw nsw i64 %iv, -1604 %exitcond.not = icmp eq i64 %iv.next, 0605 br i1 %exitcond.not, label %exit, label %loop606 607exit:608 %res = phi i64 [ %min.idx.next, %loop ]609 ret i64 %res610}611 612define i64 @test_no_vectorize_select_iv_sub(ptr %src) {613; CHECK-LABEL: define i64 @test_no_vectorize_select_iv_sub(614; CHECK-SAME: ptr [[SRC:%.*]]) {615; CHECK-NEXT: [[ENTRY:.*]]:616; CHECK-NEXT: br label %[[LOOP:.*]]617; CHECK: [[LOOP]]:618; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1000, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]619; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]620; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 40, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]621; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]622; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4623; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]624; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])625; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]626; CHECK-NEXT: [[IV_NEXT]] = sub i64 [[IV]], 1627; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 0628; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]629; CHECK: [[EXIT]]:630; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]631; CHECK-NEXT: ret i64 [[RES]]632;633entry:634 br label %loop635 636loop:637 %iv = phi i64 [ 1000, %entry ], [ %iv.next, %loop ]638 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]639 %min.val = phi i64 [ 40, %entry ], [ %min.val.next, %loop ]640 %gep = getelementptr i64, ptr %src, i64 %iv641 %l = load i64, ptr %gep642 %cmp = icmp uge i64 %min.val, %l643 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)644 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx645 %iv.next = sub i64 %iv, 1646 %exitcond.not = icmp eq i64 %iv.next, 0647 br i1 %exitcond.not, label %exit, label %loop648 649exit:650 %res = phi i64 [ %min.idx.next, %loop ]651 ret i64 %res652}653 654define i64 @test_no_vectorize_select_iv_mul(ptr %src) {655; CHECK-LABEL: define i64 @test_no_vectorize_select_iv_mul(656; CHECK-SAME: ptr [[SRC:%.*]]) {657; CHECK-NEXT: [[ENTRY:.*]]:658; CHECK-NEXT: br label %[[LOOP:.*]]659; CHECK: [[LOOP]]:660; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]661; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]662; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 30, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]663; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]664; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4665; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]666; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])667; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]668; CHECK-NEXT: [[IV_NEXT]] = mul i64 [[IV]], 2669; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 128670; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]671; CHECK: [[EXIT]]:672; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]673; CHECK-NEXT: ret i64 [[RES]]674;675entry:676 br label %loop677 678loop:679 %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop ]680 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]681 %min.val = phi i64 [ 30, %entry ], [ %min.val.next, %loop ]682 %gep = getelementptr i64, ptr %src, i64 %iv683 %l = load i64, ptr %gep684 %cmp = icmp uge i64 %min.val, %l685 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)686 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx687 %iv.next = mul i64 %iv, 2688 %exitcond.not = icmp eq i64 %iv.next, 128689 br i1 %exitcond.not, label %exit, label %loop690 691exit:692 %res = phi i64 [ %min.idx.next, %loop ]693 ret i64 %res694}695 696define i64 @test_cmp_use_find_iv_phi_twice(ptr %src, i64 %n) {697; CHECK-LABEL: define i64 @test_cmp_use_find_iv_phi_twice(698; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {699; CHECK-NEXT: [[ENTRY:.*]]:700; CHECK-NEXT: br label %[[LOOP:.*]]701; CHECK: [[LOOP]]:702; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]703; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]704; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 20, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]705; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV1]]706; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP1]], align 4707; CHECK-NEXT: [[ADD:%.*]] = add i64 [[MIN_VAL]], [[L]]708; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[ADD]]709; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])710; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV1]], i64 [[MIN_IDX]]711; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1712; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]713; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]714; CHECK: [[EXIT]]:715; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]716; CHECK-NEXT: ret i64 [[RES]]717;718entry:719 br label %loop720 721loop:722 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]723 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]724 %min.val = phi i64 [ 20, %entry ], [ %min.val.next, %loop ]725 %gep = getelementptr i64, ptr %src, i64 %iv726 %l = load i64, ptr %gep727 %add = add i64 %min.val, %l728 %cmp = icmp uge i64 %min.val, %add729 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)730 %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx731 %iv.next = add nuw nsw i64 %iv, 1732 %exitcond.not = icmp eq i64 %iv.next, %n733 br i1 %exitcond.not, label %exit, label %loop734 735exit:736 %res = phi i64 [ %min.idx.next, %loop ]737 ret i64 %res738}739 740define i64 @test_vectorize_select_umin_idx_inc(ptr %src, i64 %n) {741; CHECK-LABEL: define i64 @test_vectorize_select_umin_idx_inc(742; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {743; CHECK-NEXT: [[ENTRY:.*]]:744; CHECK-NEXT: br label %[[LOOP:.*]]745; CHECK: [[LOOP]]:746; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]747; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]748; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 140, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]749; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]750; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 4751; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]752; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1753; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])754; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV_NEXT]], i64 [[MIN_IDX]]755; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]756; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]757; CHECK: [[EXIT]]:758; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]759; CHECK-NEXT: ret i64 [[RES]]760;761entry:762 br label %loop763 764loop:765 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]766 %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]767 %min.val = phi i64 [ 140, %entry ], [ %min.val.next, %loop ]768 %gep = getelementptr i64, ptr %src, i64 %iv769 %l = load i64, ptr %gep770 %cmp = icmp uge i64 %min.val, %l771 %iv.next = add nuw nsw i64 %iv, 1772 %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)773 %min.idx.next = select i1 %cmp, i64 %iv.next, i64 %min.idx774 %exitcond.not = icmp eq i64 %iv.next, %n775 br i1 %exitcond.not, label %exit, label %loop776 777exit:778 %res = phi i64 [ %min.idx.next, %loop ]779 ret i64 %res780}781 782 783declare i64 @llvm.umin.i64(i64, i64)784declare i16 @llvm.umin.i16(i16, i16)785