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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -p loop-vectorize -enable-early-exit-vectorization -force-vector-width=4 -S %s | FileCheck --check-prefix=VF4IC4 %s3 4declare void @init_mem(ptr, i64);5 6define i64 @multi_exiting_to_different_exits_live_in_exit_values() {7; VF4IC4-LABEL: define i64 @multi_exiting_to_different_exits_live_in_exit_values() {8; VF4IC4-NEXT: [[ENTRY:.*:]]9; VF4IC4-NEXT: [[SRC:%.*]] = alloca [128 x i32], align 410; VF4IC4-NEXT: call void @init_mem(ptr [[SRC]])11; VF4IC4-NEXT: br label %[[VECTOR_PH:.*]]12; VF4IC4: [[VECTOR_PH]]:13; VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]]14; VF4IC4: [[VECTOR_BODY]]:15; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]16; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]17; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 418; VF4IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 819; VF4IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 1220; VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 421; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 422; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP12]], align 423; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP13]], align 424; VF4IC4-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], splat (i32 10)25; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD1]], splat (i32 10)26; VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD2]], splat (i32 10)27; VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD3]], splat (i32 10)28; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1629; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP2]]30; VF4IC4-NEXT: [[TMP9:%.*]] = freeze <4 x i1> [[TMP6]]31; VF4IC4-NEXT: [[TMP10:%.*]] = or <4 x i1> [[TMP14]], [[TMP9]]32; VF4IC4-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP7]]33; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP10]], [[TMP15]]34; VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP8]]35; VF4IC4-NEXT: [[TMP11:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]]36; VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP11]])37; VF4IC4-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12838; VF4IC4-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]39; VF4IC4-NEXT: br i1 [[TMP5]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]40; VF4IC4: [[MIDDLE_SPLIT]]:41; VF4IC4-NEXT: br i1 [[TMP3]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]42; VF4IC4: [[MIDDLE_BLOCK]]:43; VF4IC4-NEXT: br label %[[E2:.*]]44; VF4IC4: [[VECTOR_EARLY_EXIT]]:45; VF4IC4-NEXT: br label %[[E1:.*]]46; VF4IC4: [[E1]]:47; VF4IC4-NEXT: ret i64 048; VF4IC4: [[E2]]:49; VF4IC4-NEXT: ret i64 150;51entry:52 %src = alloca [128 x i32]53 call void @init_mem(ptr %src)54 br label %loop.header55 56loop.header:57 %iv = phi i64 [ %inc, %loop.latch ], [ 0, %entry ]58 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv59 %l = load i32, ptr %gep.src60 %c.1 = icmp eq i32 %l, 1061 br i1 %c.1, label %e1, label %loop.latch62 63loop.latch:64 %inc = add nuw i64 %iv, 165 %c.2 = icmp eq i64 %inc, 12866 br i1 %c.2, label %e2, label %loop.header, !llvm.loop !067 68e1:69 %p1 = phi i64 [ 0, %loop.header ]70 ret i64 %p171 72e2:73 %p2 = phi i64 [ 1, %loop.latch ]74 ret i64 %p275}76 77!0 = distinct !{!0, !1}78!1 = !{!"llvm.loop.interleave.count", i32 4}79;.80; VF4IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}81; VF4IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}82; VF4IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}83;.84