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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 42; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -S %s | FileCheck --check-prefix=VF4IC4 %s3 4declare void @init_mem(ptr, i64);5 6define i64 @multi_exiting_to_different_exits_live_in_exit_values() {7; VF4IC4-LABEL: define i64 @multi_exiting_to_different_exits_live_in_exit_values() {8; VF4IC4-NEXT: entry:9; VF4IC4-NEXT: [[SRC:%.*]] = alloca [128 x i32], align 410; VF4IC4-NEXT: call void @init_mem(ptr [[SRC]])11; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]12; VF4IC4: vector.ph:13; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]14; VF4IC4: vector.body:15; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]16; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]17; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 418; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 819; VF4IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 1220; VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 421; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP1]], align 422; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP2]], align 423; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP12]], align 424; VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], splat (i32 10)25; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD1]], splat (i32 10)26; VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD2]], splat (i32 10)27; VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD3]], splat (i32 10)28; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1629; VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP8]]30; VF4IC4-NEXT: [[TMP13:%.*]] = freeze <4 x i1> [[TMP6]]31; VF4IC4-NEXT: [[TMP9:%.*]] = or <4 x i1> [[TMP17]], [[TMP13]]32; VF4IC4-NEXT: [[TMP10:%.*]] = freeze <4 x i1> [[TMP7]]33; VF4IC4-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP9]], [[TMP10]]34; VF4IC4-NEXT: [[TMP16:%.*]] = freeze <4 x i1> [[TMP14]]35; VF4IC4-NEXT: [[TMP11:%.*]] = or <4 x i1> [[TMP15]], [[TMP16]]36; VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP11]])37; VF4IC4-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12838; VF4IC4-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]39; VF4IC4-NEXT: br i1 [[TMP5]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]40; VF4IC4: middle.split:41; VF4IC4-NEXT: br i1 [[TMP3]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]42; VF4IC4: middle.block:43; VF4IC4-NEXT: br label [[E2:%.*]]44; VF4IC4: vector.early.exit:45; VF4IC4-NEXT: br label [[LOOP_HEADER:%.*]]46; VF4IC4: e1:47; VF4IC4-NEXT: ret i64 048; VF4IC4: e2:49; VF4IC4-NEXT: ret i64 150;51entry:52 %src = alloca [128 x i32]53 call void @init_mem(ptr %src)54 br label %loop.header55 56loop.header:57 %iv = phi i64 [ %inc, %loop.latch ], [ 0, %entry ]58 %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv59 %l = load i32, ptr %gep.src60 %c.1 = icmp eq i32 %l, 1061 br i1 %c.1, label %e1, label %loop.latch62 63loop.latch:64 %inc = add nuw i64 %iv, 165 %c.2 = icmp eq i64 %inc, 12866 br i1 %c.2, label %e2, label %loop.header67 68e1:69 %p1 = phi i64 [ 0, %loop.header ]70 ret i64 %p171 72e2:73 %p2 = phi i64 [ 1, %loop.latch ]74 ret i64 %p275}76 77define i64 @same_exit_block_pre_inc_use1() {78; VF4IC4-LABEL: define i64 @same_exit_block_pre_inc_use1() {79; VF4IC4-NEXT: entry:80; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 181; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 182; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)83; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)84; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]85; VF4IC4: vector.ph:86; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]87; VF4IC4: vector.body:88; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]89; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]90; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]91; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 492; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 893; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 1294; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP0]], align 195; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP1]], align 196; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 197; VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP3]], align 198; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]99; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 4100; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 8101; VF4IC4-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 12102; VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1103; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1104; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP18]], align 1105; VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i8>, ptr [[TMP19]], align 1106; VF4IC4-NEXT: [[TMP13:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], [[WIDE_LOAD7]]107; VF4IC4-NEXT: [[TMP11:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD1]], [[WIDE_LOAD5]]108; VF4IC4-NEXT: [[TMP12:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], [[WIDE_LOAD6]]109; VF4IC4-NEXT: [[TMP35:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD4]], [[WIDE_LOAD8]]110; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16111; VF4IC4-NEXT: [[TMP37:%.*]] = freeze <4 x i1> [[TMP13]]112; VF4IC4-NEXT: [[TMP33:%.*]] = freeze <4 x i1> [[TMP11]]113; VF4IC4-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP37]], [[TMP33]]114; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP12]]115; VF4IC4-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP34]], [[TMP14]]116; VF4IC4-NEXT: [[TMP36:%.*]] = freeze <4 x i1> [[TMP35]]117; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP15]], [[TMP36]]118; VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])119; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64120; VF4IC4-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]121; VF4IC4-NEXT: br i1 [[TMP7]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]122; VF4IC4: middle.split:123; VF4IC4-NEXT: br i1 [[TMP5]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]124; VF4IC4: middle.block:125; VF4IC4-NEXT: br label [[LOOP_END:%.*]]126; VF4IC4: vector.early.exit:127; VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP35]], i1 false)128; VF4IC4-NEXT: [[TMP21:%.*]] = add i64 12, [[TMP20]]129; VF4IC4-NEXT: [[TMP22:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP12]], i1 false)130; VF4IC4-NEXT: [[TMP23:%.*]] = add i64 8, [[TMP22]]131; VF4IC4-NEXT: [[TMP24:%.*]] = icmp ne i64 [[TMP22]], 4132; VF4IC4-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP23]], i64 [[TMP21]]133; VF4IC4-NEXT: [[TMP26:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP11]], i1 false)134; VF4IC4-NEXT: [[TMP27:%.*]] = add i64 4, [[TMP26]]135; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP26]], 4136; VF4IC4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[TMP25]]137; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP13]], i1 false)138; VF4IC4-NEXT: [[TMP31:%.*]] = add i64 0, [[TMP30]]139; VF4IC4-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP30]], 4140; VF4IC4-NEXT: [[TMP8:%.*]] = select i1 [[TMP32]], i64 [[TMP31]], i64 [[TMP29]]141; VF4IC4-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]]142; VF4IC4-NEXT: [[TMP10:%.*]] = add i64 3, [[TMP9]]143; VF4IC4-NEXT: br label [[LOOP_END]]144; VF4IC4: loop.end:145; VF4IC4-NEXT: [[RETVAL:%.*]] = phi i64 [ 67, [[MIDDLE_BLOCK]] ], [ [[TMP10]], [[VECTOR_EARLY_EXIT]] ]146; VF4IC4-NEXT: ret i64 [[RETVAL]]147;148entry:149 %p1 = alloca [1024 x i8]150 %p2 = alloca [1024 x i8]151 call void @init_mem(ptr %p1, i64 1024)152 call void @init_mem(ptr %p2, i64 1024)153 br label %loop154 155loop:156 %iv = phi i64 [ %iv.next, %loop.inc ], [ 3, %entry ]157 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv158 %ld1 = load i8, ptr %gep.p1, align 1159 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv160 %ld2 = load i8, ptr %gep.p2, align 1161 %cmp3 = icmp eq i8 %ld1, %ld2162 br i1 %cmp3, label %loop.inc, label %loop.end163 164loop.inc:165 %iv.next = add i64 %iv, 1166 %exitcond = icmp ne i64 %iv.next, 67167 br i1 %exitcond, label %loop, label %loop.end168 169loop.end:170 %retval = phi i64 [ %iv, %loop ], [ 67, %loop.inc ]171 ret i64 %retval172}173 174define ptr @same_exit_block_pre_inc_use1_ivptr() {175; VF4IC4-LABEL: define ptr @same_exit_block_pre_inc_use1_ivptr() {176; VF4IC4-NEXT: entry:177; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1178; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)179; VF4IC4-NEXT: [[PTREND:%.*]] = getelementptr i8, ptr [[P1]], i64 1024180; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]181; VF4IC4: vector.ph:182; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]183; VF4IC4: vector.body:184; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]185; VF4IC4-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P1]], i64 [[INDEX]]186; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 4187; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 8188; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 12189; VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[NEXT_GEP]], align 1190; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1191; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1192; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1193; VF4IC4-NEXT: [[TMP17:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], splat (i8 72)194; VF4IC4-NEXT: [[TMP14:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD1]], splat (i8 72)195; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], splat (i8 72)196; VF4IC4-NEXT: [[TMP29:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], splat (i8 72)197; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16198; VF4IC4-NEXT: [[TMP35:%.*]] = freeze <4 x i1> [[TMP17]]199; VF4IC4-NEXT: [[TMP13:%.*]] = freeze <4 x i1> [[TMP14]]200; VF4IC4-NEXT: [[TMP31:%.*]] = or <4 x i1> [[TMP35]], [[TMP13]]201; VF4IC4-NEXT: [[TMP32:%.*]] = freeze <4 x i1> [[TMP28]]202; VF4IC4-NEXT: [[TMP33:%.*]] = or <4 x i1> [[TMP31]], [[TMP32]]203; VF4IC4-NEXT: [[TMP34:%.*]] = freeze <4 x i1> [[TMP29]]204; VF4IC4-NEXT: [[TMP9:%.*]] = or <4 x i1> [[TMP33]], [[TMP34]]205; VF4IC4-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP9]])206; VF4IC4-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024207; VF4IC4-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]208; VF4IC4-NEXT: br i1 [[TMP12]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]209; VF4IC4: middle.split:210; VF4IC4-NEXT: br i1 [[TMP10]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]211; VF4IC4: middle.block:212; VF4IC4-NEXT: br label [[LOOP_END:%.*]]213; VF4IC4: vector.early.exit:214; VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP29]], i1 false)215; VF4IC4-NEXT: [[TMP16:%.*]] = add i64 12, [[TMP15]]216; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP28]], i1 false)217; VF4IC4-NEXT: [[TMP18:%.*]] = add i64 8, [[TMP30]]218; VF4IC4-NEXT: [[TMP19:%.*]] = icmp ne i64 [[TMP30]], 4219; VF4IC4-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i64 [[TMP18]], i64 [[TMP16]]220; VF4IC4-NEXT: [[TMP21:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP14]], i1 false)221; VF4IC4-NEXT: [[TMP22:%.*]] = add i64 4, [[TMP21]]222; VF4IC4-NEXT: [[TMP23:%.*]] = icmp ne i64 [[TMP21]], 4223; VF4IC4-NEXT: [[TMP24:%.*]] = select i1 [[TMP23]], i64 [[TMP22]], i64 [[TMP20]]224; VF4IC4-NEXT: [[TMP25:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP17]], i1 false)225; VF4IC4-NEXT: [[TMP26:%.*]] = add i64 0, [[TMP25]]226; VF4IC4-NEXT: [[TMP27:%.*]] = icmp ne i64 [[TMP25]], 4227; VF4IC4-NEXT: [[TMP6:%.*]] = select i1 [[TMP27]], i64 [[TMP26]], i64 [[TMP24]]228; VF4IC4-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], [[TMP6]]229; VF4IC4-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P1]], i64 [[TMP7]]230; VF4IC4-NEXT: br label [[LOOP_END]]231; VF4IC4: loop.end:232; VF4IC4-NEXT: [[RETVAL:%.*]] = phi ptr [ [[PTREND]], [[MIDDLE_BLOCK]] ], [ [[TMP8]], [[VECTOR_EARLY_EXIT]] ]233; VF4IC4-NEXT: ret ptr [[RETVAL]]234;235entry:236 %p1 = alloca [1024 x i8]237 call void @init_mem(ptr %p1, i64 1024)238 %ptrend = getelementptr i8, ptr %p1, i64 1024239 br label %loop240 241loop:242 %ptr = phi ptr [ %ptr.next, %loop.inc ], [ %p1, %entry ]243 %ld1 = load i8, ptr %ptr, align 1244 %cmp3 = icmp eq i8 %ld1, 72245 br i1 %cmp3, label %loop.inc, label %loop.end246 247loop.inc:248 %ptr.next = getelementptr inbounds i8, ptr %ptr, i64 1249 %exitcond = icmp ne ptr %ptr.next, %ptrend250 br i1 %exitcond, label %loop, label %loop.end251 252loop.end:253 %retval = phi ptr [ %ptr, %loop ], [ %ptrend, %loop.inc ]254 ret ptr %retval255}256 257define i64 @same_exit_block_post_inc_use() {258; VF4IC4-LABEL: define i64 @same_exit_block_post_inc_use() {259; VF4IC4-NEXT: entry:260; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1261; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1262; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)263; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)264; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]265; VF4IC4: vector.ph:266; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]267; VF4IC4: vector.body:268; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]269; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]270; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]271; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4272; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8273; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 12274; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1275; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1276; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1277; VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1278; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]279; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 4280; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 8281; VF4IC4-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 12282; VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1283; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1284; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP18]], align 1285; VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i8>, ptr [[TMP19]], align 1286; VF4IC4-NEXT: [[TMP13:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], [[WIDE_LOAD7]]287; VF4IC4-NEXT: [[TMP11:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD1]], [[WIDE_LOAD5]]288; VF4IC4-NEXT: [[TMP12:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], [[WIDE_LOAD6]]289; VF4IC4-NEXT: [[TMP35:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD4]], [[WIDE_LOAD8]]290; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16291; VF4IC4-NEXT: [[TMP37:%.*]] = freeze <4 x i1> [[TMP13]]292; VF4IC4-NEXT: [[TMP33:%.*]] = freeze <4 x i1> [[TMP11]]293; VF4IC4-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP37]], [[TMP33]]294; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP12]]295; VF4IC4-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP34]], [[TMP14]]296; VF4IC4-NEXT: [[TMP36:%.*]] = freeze <4 x i1> [[TMP35]]297; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP15]], [[TMP36]]298; VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])299; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64300; VF4IC4-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]301; VF4IC4-NEXT: br i1 [[TMP7]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]302; VF4IC4: middle.split:303; VF4IC4-NEXT: br i1 [[TMP5]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]304; VF4IC4: middle.block:305; VF4IC4-NEXT: br label [[LOOP_END:%.*]]306; VF4IC4: vector.early.exit:307; VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP35]], i1 false)308; VF4IC4-NEXT: [[TMP21:%.*]] = add i64 12, [[TMP20]]309; VF4IC4-NEXT: [[TMP22:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP12]], i1 false)310; VF4IC4-NEXT: [[TMP23:%.*]] = add i64 8, [[TMP22]]311; VF4IC4-NEXT: [[TMP24:%.*]] = icmp ne i64 [[TMP22]], 4312; VF4IC4-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP23]], i64 [[TMP21]]313; VF4IC4-NEXT: [[TMP26:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP11]], i1 false)314; VF4IC4-NEXT: [[TMP27:%.*]] = add i64 4, [[TMP26]]315; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP26]], 4316; VF4IC4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[TMP25]]317; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP13]], i1 false)318; VF4IC4-NEXT: [[TMP31:%.*]] = add i64 0, [[TMP30]]319; VF4IC4-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP30]], 4320; VF4IC4-NEXT: [[TMP8:%.*]] = select i1 [[TMP32]], i64 [[TMP31]], i64 [[TMP29]]321; VF4IC4-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]]322; VF4IC4-NEXT: [[TMP10:%.*]] = add i64 3, [[TMP9]]323; VF4IC4-NEXT: br label [[LOOP_END]]324; VF4IC4: loop.end:325; VF4IC4-NEXT: [[RETVAL:%.*]] = phi i64 [ 67, [[MIDDLE_BLOCK]] ], [ [[TMP10]], [[VECTOR_EARLY_EXIT]] ]326; VF4IC4-NEXT: ret i64 [[RETVAL]]327;328entry:329 %p1 = alloca [1024 x i8]330 %p2 = alloca [1024 x i8]331 call void @init_mem(ptr %p1, i64 1024)332 call void @init_mem(ptr %p2, i64 1024)333 br label %loop334 335loop:336 %iv = phi i64 [ %iv.next, %loop.inc ], [ 3, %entry ]337 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv338 %ld1 = load i8, ptr %gep.p1, align 1339 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv340 %ld2 = load i8, ptr %gep.p2, align 1341 %cmp3 = icmp eq i8 %ld1, %ld2342 br i1 %cmp3, label %loop.inc, label %loop.end343 344loop.inc:345 %iv.next = add i64 %iv, 1346 %exitcond = icmp ne i64 %iv.next, 67347 br i1 %exitcond, label %loop, label %loop.end348 349loop.end:350 %retval = phi i64 [ %iv, %loop ], [ %iv.next, %loop.inc ]351 ret i64 %retval352}353 354define i64 @diff_exit_block_pre_inc_use1() {355; VF4IC4-LABEL: define i64 @diff_exit_block_pre_inc_use1() {356; VF4IC4-NEXT: entry:357; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1358; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1359; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)360; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)361; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]362; VF4IC4: vector.ph:363; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]364; VF4IC4: vector.body:365; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]366; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]367; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]368; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4369; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8370; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 12371; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1372; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1373; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1374; VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1375; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]376; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 4377; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 8378; VF4IC4-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 12379; VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1380; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1381; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP18]], align 1382; VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i8>, ptr [[TMP19]], align 1383; VF4IC4-NEXT: [[TMP13:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], [[WIDE_LOAD7]]384; VF4IC4-NEXT: [[TMP11:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD1]], [[WIDE_LOAD5]]385; VF4IC4-NEXT: [[TMP12:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], [[WIDE_LOAD6]]386; VF4IC4-NEXT: [[TMP35:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD4]], [[WIDE_LOAD8]]387; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16388; VF4IC4-NEXT: [[TMP37:%.*]] = freeze <4 x i1> [[TMP13]]389; VF4IC4-NEXT: [[TMP33:%.*]] = freeze <4 x i1> [[TMP11]]390; VF4IC4-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP37]], [[TMP33]]391; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP12]]392; VF4IC4-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP34]], [[TMP14]]393; VF4IC4-NEXT: [[TMP36:%.*]] = freeze <4 x i1> [[TMP35]]394; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP15]], [[TMP36]]395; VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])396; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64397; VF4IC4-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]398; VF4IC4-NEXT: br i1 [[TMP7]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]399; VF4IC4: middle.split:400; VF4IC4-NEXT: br i1 [[TMP5]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]401; VF4IC4: middle.block:402; VF4IC4-NEXT: br label [[LOOP_END:%.*]]403; VF4IC4: vector.early.exit:404; VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP35]], i1 false)405; VF4IC4-NEXT: [[TMP21:%.*]] = add i64 12, [[TMP20]]406; VF4IC4-NEXT: [[TMP22:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP12]], i1 false)407; VF4IC4-NEXT: [[TMP23:%.*]] = add i64 8, [[TMP22]]408; VF4IC4-NEXT: [[TMP24:%.*]] = icmp ne i64 [[TMP22]], 4409; VF4IC4-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP23]], i64 [[TMP21]]410; VF4IC4-NEXT: [[TMP26:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP11]], i1 false)411; VF4IC4-NEXT: [[TMP27:%.*]] = add i64 4, [[TMP26]]412; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP26]], 4413; VF4IC4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[TMP25]]414; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP13]], i1 false)415; VF4IC4-NEXT: [[TMP31:%.*]] = add i64 0, [[TMP30]]416; VF4IC4-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP30]], 4417; VF4IC4-NEXT: [[TMP8:%.*]] = select i1 [[TMP32]], i64 [[TMP31]], i64 [[TMP29]]418; VF4IC4-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]]419; VF4IC4-NEXT: [[TMP10:%.*]] = add i64 3, [[TMP9]]420; VF4IC4-NEXT: br label [[LOOP:%.*]]421; VF4IC4: loop.early.exit:422; VF4IC4-NEXT: ret i64 [[TMP10]]423; VF4IC4: loop.end:424; VF4IC4-NEXT: ret i64 67425;426entry:427 %p1 = alloca [1024 x i8]428 %p2 = alloca [1024 x i8]429 call void @init_mem(ptr %p1, i64 1024)430 call void @init_mem(ptr %p2, i64 1024)431 br label %loop432 433loop:434 %iv = phi i64 [ %iv.next, %loop.inc ], [ 3, %entry ]435 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv436 %ld1 = load i8, ptr %gep.p1, align 1437 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv438 %ld2 = load i8, ptr %gep.p2, align 1439 %cmp3 = icmp eq i8 %ld1, %ld2440 br i1 %cmp3, label %loop.inc, label %loop.early.exit441 442loop.inc:443 %iv.next = add i64 %iv, 1444 %exitcond = icmp ne i64 %iv.next, 67445 br i1 %exitcond, label %loop, label %loop.end446 447loop.early.exit:448 %retval1 = phi i64 [ %iv, %loop ]449 ret i64 %retval1450 451loop.end:452 %retval2 = phi i64 [ 67, %loop.inc ]453 ret i64 %retval2454}455 456define i64 @diff_exit_block_post_inc_use1() {457; VF4IC4-LABEL: define i64 @diff_exit_block_post_inc_use1() {458; VF4IC4-NEXT: entry:459; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1460; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1461; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)462; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)463; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]464; VF4IC4: vector.ph:465; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]466; VF4IC4: vector.body:467; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]468; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]469; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]470; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4471; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8472; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 12473; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1474; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1475; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1476; VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1477; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]478; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 4479; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 8480; VF4IC4-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 12481; VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1482; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1483; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP18]], align 1484; VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i8>, ptr [[TMP19]], align 1485; VF4IC4-NEXT: [[TMP13:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], [[WIDE_LOAD7]]486; VF4IC4-NEXT: [[TMP11:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD1]], [[WIDE_LOAD5]]487; VF4IC4-NEXT: [[TMP12:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], [[WIDE_LOAD6]]488; VF4IC4-NEXT: [[TMP35:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD4]], [[WIDE_LOAD8]]489; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16490; VF4IC4-NEXT: [[TMP37:%.*]] = freeze <4 x i1> [[TMP13]]491; VF4IC4-NEXT: [[TMP33:%.*]] = freeze <4 x i1> [[TMP11]]492; VF4IC4-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP37]], [[TMP33]]493; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP12]]494; VF4IC4-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP34]], [[TMP14]]495; VF4IC4-NEXT: [[TMP36:%.*]] = freeze <4 x i1> [[TMP35]]496; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP15]], [[TMP36]]497; VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])498; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64499; VF4IC4-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]500; VF4IC4-NEXT: br i1 [[TMP7]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]501; VF4IC4: middle.split:502; VF4IC4-NEXT: br i1 [[TMP5]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]503; VF4IC4: middle.block:504; VF4IC4-NEXT: br label [[LOOP_END:%.*]]505; VF4IC4: vector.early.exit:506; VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP35]], i1 false)507; VF4IC4-NEXT: [[TMP21:%.*]] = add i64 12, [[TMP20]]508; VF4IC4-NEXT: [[TMP22:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP12]], i1 false)509; VF4IC4-NEXT: [[TMP23:%.*]] = add i64 8, [[TMP22]]510; VF4IC4-NEXT: [[TMP24:%.*]] = icmp ne i64 [[TMP22]], 4511; VF4IC4-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP23]], i64 [[TMP21]]512; VF4IC4-NEXT: [[TMP26:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP11]], i1 false)513; VF4IC4-NEXT: [[TMP27:%.*]] = add i64 4, [[TMP26]]514; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP26]], 4515; VF4IC4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[TMP25]]516; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP13]], i1 false)517; VF4IC4-NEXT: [[TMP31:%.*]] = add i64 0, [[TMP30]]518; VF4IC4-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP30]], 4519; VF4IC4-NEXT: [[TMP8:%.*]] = select i1 [[TMP32]], i64 [[TMP31]], i64 [[TMP29]]520; VF4IC4-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]]521; VF4IC4-NEXT: [[TMP10:%.*]] = add i64 3, [[TMP9]]522; VF4IC4-NEXT: br label [[LOOP:%.*]]523; VF4IC4: loop.early.exit:524; VF4IC4-NEXT: ret i64 [[TMP10]]525; VF4IC4: loop.end:526; VF4IC4-NEXT: ret i64 67527;528entry:529 %p1 = alloca [1024 x i8]530 %p2 = alloca [1024 x i8]531 call void @init_mem(ptr %p1, i64 1024)532 call void @init_mem(ptr %p2, i64 1024)533 br label %loop534 535loop:536 %iv = phi i64 [ %iv.next, %loop.inc ], [ 3, %entry ]537 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv538 %ld1 = load i8, ptr %gep.p1, align 1539 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv540 %ld2 = load i8, ptr %gep.p2, align 1541 %cmp3 = icmp eq i8 %ld1, %ld2542 br i1 %cmp3, label %loop.inc, label %loop.early.exit543 544loop.inc:545 %iv.next = add i64 %iv, 1546 %exitcond = icmp ne i64 %iv.next, 67547 br i1 %exitcond, label %loop, label %loop.end548 549loop.early.exit:550 %retval1 = phi i64 [ %iv, %loop ]551 ret i64 %retval1552 553loop.end:554 %retval2 = phi i64 [ %iv.next, %loop.inc ]555 ret i64 %retval2556}557 558define i64 @same_exit_block_pre_inc_use1_reverse() {559; VF4IC4-LABEL: define i64 @same_exit_block_pre_inc_use1_reverse() {560; VF4IC4-NEXT: entry:561; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1562; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1563; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)564; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)565; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]566; VF4IC4: vector.ph:567; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]568; VF4IC4: vector.body:569; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]570; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]571; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]572; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 0573; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 -3574; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -4575; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 -3576; VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -8577; VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 -3578; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -12579; VF4IC4-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 -3580; VF4IC4-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1581; VF4IC4-NEXT: [[REVERSE14:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD13]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>582; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1583; VF4IC4-NEXT: [[REVERSE2:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD1]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>584; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP6]], align 1585; VF4IC4-NEXT: [[REVERSE4:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD3]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>586; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP27]], align 1587; VF4IC4-NEXT: [[REVERSE6:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD5]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>588; VF4IC4-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]589; VF4IC4-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[TMP25]], i64 0590; VF4IC4-NEXT: [[TMP46:%.*]] = getelementptr inbounds i8, ptr [[TMP26]], i64 -3591; VF4IC4-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[TMP25]], i64 -4592; VF4IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[TMP41]], i64 -3593; VF4IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[TMP25]], i64 -8594; VF4IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP14]], i64 -3595; VF4IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[TMP25]], i64 -12596; VF4IC4-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, ptr [[TMP16]], i64 -3597; VF4IC4-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x i8>, ptr [[TMP46]], align 1598; VF4IC4-NEXT: [[REVERSE15:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD14]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>599; VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i8>, ptr [[TMP13]], align 1600; VF4IC4-NEXT: [[REVERSE10:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD9]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>601; VF4IC4-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i8>, ptr [[TMP15]], align 1602; VF4IC4-NEXT: [[REVERSE12:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD11]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>603; VF4IC4-NEXT: [[WIDE_LOAD15:%.*]] = load <4 x i8>, ptr [[TMP42]], align 1604; VF4IC4-NEXT: [[REVERSE16:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD15]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>605; VF4IC4-NEXT: [[TMP21:%.*]] = icmp ne <4 x i8> [[REVERSE14]], [[REVERSE15]]606; VF4IC4-NEXT: [[TMP19:%.*]] = icmp ne <4 x i8> [[REVERSE2]], [[REVERSE10]]607; VF4IC4-NEXT: [[TMP20:%.*]] = icmp ne <4 x i8> [[REVERSE4]], [[REVERSE12]]608; VF4IC4-NEXT: [[TMP43:%.*]] = icmp ne <4 x i8> [[REVERSE6]], [[REVERSE16]]609; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16610; VF4IC4-NEXT: [[TMP48:%.*]] = freeze <4 x i1> [[TMP21]]611; VF4IC4-NEXT: [[TMP22:%.*]] = freeze <4 x i1> [[TMP19]]612; VF4IC4-NEXT: [[TMP23:%.*]] = or <4 x i1> [[TMP48]], [[TMP22]]613; VF4IC4-NEXT: [[TMP44:%.*]] = freeze <4 x i1> [[TMP20]]614; VF4IC4-NEXT: [[TMP45:%.*]] = or <4 x i1> [[TMP23]], [[TMP44]]615; VF4IC4-NEXT: [[TMP47:%.*]] = freeze <4 x i1> [[TMP43]]616; VF4IC4-NEXT: [[TMP24:%.*]] = or <4 x i1> [[TMP45]], [[TMP47]]617; VF4IC4-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP24]])618; VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1008619; VF4IC4-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]620; VF4IC4-NEXT: br i1 [[TMP9]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]621; VF4IC4: middle.split:622; VF4IC4-NEXT: br i1 [[TMP7]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]623; VF4IC4: middle.block:624; VF4IC4-NEXT: br label [[SCALAR_PH:%.*]]625; VF4IC4: vector.early.exit:626; VF4IC4-NEXT: [[TMP28:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP43]], i1 false)627; VF4IC4-NEXT: [[TMP29:%.*]] = add i64 12, [[TMP28]]628; VF4IC4-NEXT: [[TMP30:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP20]], i1 false)629; VF4IC4-NEXT: [[TMP31:%.*]] = add i64 8, [[TMP30]]630; VF4IC4-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP30]], 4631; VF4IC4-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP31]], i64 [[TMP29]]632; VF4IC4-NEXT: [[TMP34:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP19]], i1 false)633; VF4IC4-NEXT: [[TMP35:%.*]] = add i64 4, [[TMP34]]634; VF4IC4-NEXT: [[TMP36:%.*]] = icmp ne i64 [[TMP34]], 4635; VF4IC4-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP35]], i64 [[TMP33]]636; VF4IC4-NEXT: [[TMP38:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP21]], i1 false)637; VF4IC4-NEXT: [[TMP39:%.*]] = add i64 0, [[TMP38]]638; VF4IC4-NEXT: [[TMP40:%.*]] = icmp ne i64 [[TMP38]], 4639; VF4IC4-NEXT: [[TMP10:%.*]] = select i1 [[TMP40]], i64 [[TMP39]], i64 [[TMP37]]640; VF4IC4-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], [[TMP10]]641; VF4IC4-NEXT: [[TMP12:%.*]] = sub i64 1023, [[TMP11]]642; VF4IC4-NEXT: br label [[LOOP_END:%.*]]643; VF4IC4: scalar.ph:644; VF4IC4-NEXT: br label [[LOOP:%.*]]645; VF4IC4: loop:646; VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP_INC:%.*]] ], [ 15, [[SCALAR_PH]] ]647; VF4IC4-NEXT: [[GEP_P1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]648; VF4IC4-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP_P1]], align 1649; VF4IC4-NEXT: [[GEP_P2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]650; VF4IC4-NEXT: [[LD2:%.*]] = load i8, ptr [[GEP_P2]], align 1651; VF4IC4-NEXT: [[CMP3:%.*]] = icmp eq i8 [[LD1]], [[LD2]]652; VF4IC4-NEXT: br i1 [[CMP3]], label [[LOOP_INC]], label [[LOOP_END]]653; VF4IC4: loop.inc:654; VF4IC4-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1655; VF4IC4-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 0656; VF4IC4-NEXT: br i1 [[EXITCOND]], label [[LOOP_END]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]657; VF4IC4: loop.end:658; VF4IC4-NEXT: [[RETVAL:%.*]] = phi i64 [ [[IV]], [[LOOP]] ], [ 1024, [[LOOP_INC]] ], [ [[TMP12]], [[VECTOR_EARLY_EXIT]] ]659; VF4IC4-NEXT: ret i64 [[RETVAL]]660;661entry:662 %p1 = alloca [1024 x i8]663 %p2 = alloca [1024 x i8]664 call void @init_mem(ptr %p1, i64 1024)665 call void @init_mem(ptr %p2, i64 1024)666 br label %loop667 668loop:669 %iv = phi i64 [ %iv.next, %loop.inc ], [ 1023, %entry ]670 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv671 %ld1 = load i8, ptr %gep.p1, align 1672 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv673 %ld2 = load i8, ptr %gep.p2, align 1674 %cmp3 = icmp eq i8 %ld1, %ld2675 br i1 %cmp3, label %loop.inc, label %loop.end676 677loop.inc:678 %iv.next = add i64 %iv, -1679 %exitcond = icmp eq i64 %iv.next, 0680 br i1 %exitcond, label %loop.end, label %loop681 682loop.end:683 %retval = phi i64 [ %iv, %loop ], [ 1024, %loop.inc ]684 ret i64 %retval685}686 687; FIXME: Extracts incorrect lane if early exit is taken.688define i8 @same_exit_block_use_loaded_value() {689; VF4IC4-LABEL: define i8 @same_exit_block_use_loaded_value() {690; VF4IC4-NEXT: entry:691; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1692; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1693; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)694; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)695; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]696; VF4IC4: vector.ph:697; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]698; VF4IC4: vector.body:699; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]700; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]701; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4702; VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8703; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 12704; VF4IC4-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1705; VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1706; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1707; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1708; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]709; VF4IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 4710; VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 8711; VF4IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 12712; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1713; VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i8>, ptr [[TMP9]], align 1714; VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i8>, ptr [[TMP10]], align 1715; VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i8>, ptr [[TMP15]], align 1716; VF4IC4-NEXT: [[TMP12:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD2]], [[WIDE_LOAD6]]717; VF4IC4-NEXT: [[TMP29:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD4]], [[WIDE_LOAD8]]718; VF4IC4-NEXT: [[TMP11:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD5]], [[WIDE_LOAD9]]719; VF4IC4-NEXT: [[TMP17:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD3]], [[WIDE_LOAD7]]720; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16721; VF4IC4-NEXT: [[TMP43:%.*]] = freeze <4 x i1> [[TMP12]]722; VF4IC4-NEXT: [[TMP18:%.*]] = freeze <4 x i1> [[TMP29]]723; VF4IC4-NEXT: [[TMP13:%.*]] = or <4 x i1> [[TMP43]], [[TMP18]]724; VF4IC4-NEXT: [[TMP14:%.*]] = freeze <4 x i1> [[TMP11]]725; VF4IC4-NEXT: [[TMP19:%.*]] = or <4 x i1> [[TMP13]], [[TMP14]]726; VF4IC4-NEXT: [[TMP30:%.*]] = freeze <4 x i1> [[TMP17]]727; VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP19]], [[TMP30]]728; VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])729; VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024730; VF4IC4-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]731; VF4IC4-NEXT: br i1 [[TMP7]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]732; VF4IC4: middle.split:733; VF4IC4-NEXT: br i1 [[TMP5]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]734; VF4IC4: middle.block:735; VF4IC4-NEXT: br label [[LOOP_END:%.*]]736; VF4IC4: vector.early.exit:737; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP17]], i1 false)738; VF4IC4-NEXT: [[TMP20:%.*]] = add i64 12, [[FIRST_ACTIVE_LANE]]739; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE8:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP11]], i1 false)740; VF4IC4-NEXT: [[TMP21:%.*]] = add i64 8, [[FIRST_ACTIVE_LANE8]]741; VF4IC4-NEXT: [[TMP22:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE8]], 4742; VF4IC4-NEXT: [[TMP23:%.*]] = select i1 [[TMP22]], i64 [[TMP21]], i64 [[TMP20]]743; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE9:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP29]], i1 false)744; VF4IC4-NEXT: [[TMP24:%.*]] = add i64 4, [[FIRST_ACTIVE_LANE9]]745; VF4IC4-NEXT: [[TMP25:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE9]], 4746; VF4IC4-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], i64 [[TMP24]], i64 [[TMP23]]747; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE1:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP12]], i1 false)748; VF4IC4-NEXT: [[TMP27:%.*]] = add i64 0, [[FIRST_ACTIVE_LANE1]]749; VF4IC4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE1]], 4750; VF4IC4-NEXT: [[TMP8:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[TMP26]]751; VF4IC4-NEXT: [[EARLY_EXIT_VALUE:%.*]] = extractelement <4 x i8> [[WIDE_LOAD2]], i64 [[TMP8]]752; VF4IC4-NEXT: [[TMP31:%.*]] = sub i64 [[TMP8]], 4753; VF4IC4-NEXT: [[TMP32:%.*]] = extractelement <4 x i8> [[WIDE_LOAD4]], i64 [[TMP31]]754; VF4IC4-NEXT: [[TMP33:%.*]] = icmp uge i64 [[TMP8]], 4755; VF4IC4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i8 [[TMP32]], i8 [[EARLY_EXIT_VALUE]]756; VF4IC4-NEXT: [[TMP35:%.*]] = sub i64 [[TMP8]], 8757; VF4IC4-NEXT: [[TMP36:%.*]] = extractelement <4 x i8> [[WIDE_LOAD5]], i64 [[TMP35]]758; VF4IC4-NEXT: [[TMP37:%.*]] = icmp uge i64 [[TMP8]], 8759; VF4IC4-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i8 [[TMP36]], i8 [[TMP34]]760; VF4IC4-NEXT: [[TMP39:%.*]] = sub i64 [[TMP8]], 12761; VF4IC4-NEXT: [[TMP40:%.*]] = extractelement <4 x i8> [[WIDE_LOAD3]], i64 [[TMP39]]762; VF4IC4-NEXT: [[TMP41:%.*]] = icmp uge i64 [[TMP8]], 12763; VF4IC4-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i8 [[TMP40]], i8 [[TMP38]]764; VF4IC4-NEXT: br label [[LOOP_END]]765; VF4IC4: loop.end:766; VF4IC4-NEXT: [[RETVAL:%.*]] = phi i8 [ -1, [[MIDDLE_BLOCK]] ], [ [[TMP42]], [[VECTOR_EARLY_EXIT]] ]767; VF4IC4-NEXT: ret i8 [[RETVAL]]768;769entry:770 %p1 = alloca [1024 x i8]771 %p2 = alloca [1024 x i8]772 call void @init_mem(ptr %p1, i64 1024)773 call void @init_mem(ptr %p2, i64 1024)774 br label %loop775 776loop:777 %iv = phi i64 [ %iv.next, %loop.inc ], [ 0, %entry ]778 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv779 %ld1 = load i8, ptr %gep.p1, align 1780 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv781 %ld2 = load i8, ptr %gep.p2, align 1782 %cmp3 = icmp eq i8 %ld1, %ld2783 br i1 %cmp3, label %loop.inc, label %loop.end784 785loop.inc:786 %iv.next = add i64 %iv, 1787 %exitcond = icmp eq i64 %iv.next, 1024788 br i1 %exitcond, label %loop.end, label %loop789 790loop.end:791 %retval = phi i8 [ %ld1, %loop ], [ -1, %loop.inc ]792 ret i8 %retval793}794 795; FIXME: Extracts incorrect lane if early exit is taken.796define i8 @same_exit_block_reverse_use_loaded_value() {797; VF4IC4-LABEL: define i8 @same_exit_block_reverse_use_loaded_value() {798; VF4IC4-NEXT: entry:799; VF4IC4-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1800; VF4IC4-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1801; VF4IC4-NEXT: call void @init_mem(ptr [[P1]], i64 1024)802; VF4IC4-NEXT: call void @init_mem(ptr [[P2]], i64 1024)803; VF4IC4-NEXT: br label [[VECTOR_PH:%.*]]804; VF4IC4: vector.ph:805; VF4IC4-NEXT: br label [[VECTOR_BODY:%.*]]806; VF4IC4: vector.body:807; VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]808; VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]809; VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]810; VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 0811; VF4IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 -3812; VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -4813; VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i64 -3814; VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -8815; VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 -3816; VF4IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 -12817; VF4IC4-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 -3818; VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i8>, ptr [[TMP8]], align 1819; VF4IC4-NEXT: [[REVERSE6:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD5]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>820; VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP4]], align 1821; VF4IC4-NEXT: [[REVERSE2:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD1]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>822; VF4IC4-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP6]], align 1823; VF4IC4-NEXT: [[REVERSE4:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD3]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>824; VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i8>, ptr [[TMP11]], align 1825; VF4IC4-NEXT: [[REVERSE7:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD6]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>826; VF4IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]827; VF4IC4-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 0828; VF4IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP38]], i64 -3829; VF4IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 -4830; VF4IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i64 -3831; VF4IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 -8832; VF4IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP14]], i64 -3833; VF4IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[TMP9]], i64 -12834; VF4IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[TMP16]], i64 -3835; VF4IC4-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x i8>, ptr [[TMP17]], align 1836; VF4IC4-NEXT: [[REVERSE14:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD13]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>837; VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i8>, ptr [[TMP13]], align 1838; VF4IC4-NEXT: [[REVERSE10:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD9]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>839; VF4IC4-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i8>, ptr [[TMP15]], align 1840; VF4IC4-NEXT: [[REVERSE12:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD11]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>841; VF4IC4-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x i8>, ptr [[TMP18]], align 1842; VF4IC4-NEXT: [[REVERSE15:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD14]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>843; VF4IC4-NEXT: [[TMP21:%.*]] = icmp ne <4 x i8> [[REVERSE6]], [[REVERSE14]]844; VF4IC4-NEXT: [[TMP19:%.*]] = icmp ne <4 x i8> [[REVERSE2]], [[REVERSE10]]845; VF4IC4-NEXT: [[TMP20:%.*]] = icmp ne <4 x i8> [[REVERSE4]], [[REVERSE12]]846; VF4IC4-NEXT: [[TMP37:%.*]] = icmp ne <4 x i8> [[REVERSE7]], [[REVERSE15]]847; VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16848; VF4IC4-NEXT: [[TMP54:%.*]] = freeze <4 x i1> [[TMP21]]849; VF4IC4-NEXT: [[TMP22:%.*]] = freeze <4 x i1> [[TMP19]]850; VF4IC4-NEXT: [[TMP23:%.*]] = or <4 x i1> [[TMP54]], [[TMP22]]851; VF4IC4-NEXT: [[TMP51:%.*]] = freeze <4 x i1> [[TMP20]]852; VF4IC4-NEXT: [[TMP52:%.*]] = or <4 x i1> [[TMP23]], [[TMP51]]853; VF4IC4-NEXT: [[TMP53:%.*]] = freeze <4 x i1> [[TMP37]]854; VF4IC4-NEXT: [[TMP24:%.*]] = or <4 x i1> [[TMP52]], [[TMP53]]855; VF4IC4-NEXT: [[TMP25:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP24]])856; VF4IC4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1008857; VF4IC4-NEXT: [[TMP27:%.*]] = or i1 [[TMP25]], [[TMP26]]858; VF4IC4-NEXT: br i1 [[TMP27]], label [[MIDDLE_SPLIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]859; VF4IC4: middle.split:860; VF4IC4-NEXT: br i1 [[TMP25]], label [[VECTOR_EARLY_EXIT:%.*]], label [[MIDDLE_BLOCK:%.*]]861; VF4IC4: middle.block:862; VF4IC4-NEXT: br label [[SCALAR_PH:%.*]]863; VF4IC4: vector.early.exit:864; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP37]], i1 false)865; VF4IC4-NEXT: [[TMP28:%.*]] = add i64 12, [[FIRST_ACTIVE_LANE]]866; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE15:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP20]], i1 false)867; VF4IC4-NEXT: [[TMP29:%.*]] = add i64 8, [[FIRST_ACTIVE_LANE15]]868; VF4IC4-NEXT: [[TMP30:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE15]], 4869; VF4IC4-NEXT: [[TMP31:%.*]] = select i1 [[TMP30]], i64 [[TMP29]], i64 [[TMP28]]870; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE16:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP19]], i1 false)871; VF4IC4-NEXT: [[TMP32:%.*]] = add i64 4, [[FIRST_ACTIVE_LANE16]]872; VF4IC4-NEXT: [[TMP33:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE16]], 4873; VF4IC4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[TMP32]], i64 [[TMP31]]874; VF4IC4-NEXT: [[FIRST_ACTIVE_LANE1:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP21]], i1 false)875; VF4IC4-NEXT: [[TMP35:%.*]] = add i64 0, [[FIRST_ACTIVE_LANE1]]876; VF4IC4-NEXT: [[TMP36:%.*]] = icmp ne i64 [[FIRST_ACTIVE_LANE1]], 4877; VF4IC4-NEXT: [[TMP10:%.*]] = select i1 [[TMP36]], i64 [[TMP35]], i64 [[TMP34]]878; VF4IC4-NEXT: [[EARLY_EXIT_VALUE:%.*]] = extractelement <4 x i8> [[REVERSE6]], i64 [[TMP10]]879; VF4IC4-NEXT: [[TMP39:%.*]] = sub i64 [[TMP10]], 4880; VF4IC4-NEXT: [[TMP40:%.*]] = extractelement <4 x i8> [[REVERSE2]], i64 [[TMP39]]881; VF4IC4-NEXT: [[TMP41:%.*]] = icmp uge i64 [[TMP10]], 4882; VF4IC4-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i8 [[TMP40]], i8 [[EARLY_EXIT_VALUE]]883; VF4IC4-NEXT: [[TMP43:%.*]] = sub i64 [[TMP10]], 8884; VF4IC4-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[REVERSE4]], i64 [[TMP43]]885; VF4IC4-NEXT: [[TMP45:%.*]] = icmp uge i64 [[TMP10]], 8886; VF4IC4-NEXT: [[TMP46:%.*]] = select i1 [[TMP45]], i8 [[TMP44]], i8 [[TMP42]]887; VF4IC4-NEXT: [[TMP47:%.*]] = sub i64 [[TMP10]], 12888; VF4IC4-NEXT: [[TMP48:%.*]] = extractelement <4 x i8> [[REVERSE7]], i64 [[TMP47]]889; VF4IC4-NEXT: [[TMP49:%.*]] = icmp uge i64 [[TMP10]], 12890; VF4IC4-NEXT: [[TMP50:%.*]] = select i1 [[TMP49]], i8 [[TMP48]], i8 [[TMP46]]891; VF4IC4-NEXT: br label [[LOOP_END:%.*]]892; VF4IC4: scalar.ph:893; VF4IC4-NEXT: br label [[LOOP:%.*]]894; VF4IC4: loop:895; VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP_INC:%.*]] ], [ 15, [[SCALAR_PH]] ]896; VF4IC4-NEXT: [[GEP_P1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]897; VF4IC4-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP_P1]], align 1898; VF4IC4-NEXT: [[GEP_P2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]899; VF4IC4-NEXT: [[LD2:%.*]] = load i8, ptr [[GEP_P2]], align 1900; VF4IC4-NEXT: [[CMP3:%.*]] = icmp eq i8 [[LD1]], [[LD2]]901; VF4IC4-NEXT: br i1 [[CMP3]], label [[LOOP_INC]], label [[LOOP_END]]902; VF4IC4: loop.inc:903; VF4IC4-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1904; VF4IC4-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 0905; VF4IC4-NEXT: br i1 [[EXITCOND]], label [[LOOP_END]], label [[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]906; VF4IC4: loop.end:907; VF4IC4-NEXT: [[RETVAL:%.*]] = phi i8 [ [[LD1]], [[LOOP]] ], [ -1, [[LOOP_INC]] ], [ [[TMP50]], [[VECTOR_EARLY_EXIT]] ]908; VF4IC4-NEXT: ret i8 [[RETVAL]]909;910entry:911 %p1 = alloca [1024 x i8]912 %p2 = alloca [1024 x i8]913 call void @init_mem(ptr %p1, i64 1024)914 call void @init_mem(ptr %p2, i64 1024)915 br label %loop916 917loop:918 %iv = phi i64 [ %iv.next, %loop.inc ], [ 1023, %entry ]919 %gep.p1 = getelementptr inbounds i8, ptr %p1, i64 %iv920 %ld1 = load i8, ptr %gep.p1, align 1921 %gep.p2 = getelementptr inbounds i8, ptr %p2, i64 %iv922 %ld2 = load i8, ptr %gep.p2, align 1923 %cmp3 = icmp eq i8 %ld1, %ld2924 br i1 %cmp3, label %loop.inc, label %loop.end925 926loop.inc:927 %iv.next = add i64 %iv, -1928 %exitcond = icmp eq i64 %iv.next, 0929 br i1 %exitcond, label %loop.end, label %loop930 931loop.end:932 %retval = phi i8 [ %ld1, %loop ], [ -1, %loop.inc ]933 ret i8 %retval934}935