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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5 6define i32 @test_icmp_constant_op_zext(ptr %dst) {7; CHECK-LABEL: define i32 @test_icmp_constant_op_zext(8; CHECK-SAME: ptr [[DST:%.*]]) {9; CHECK-NEXT: entry:10; CHECK-NEXT: br label [[VECTOR_PH:%.*]]11; CHECK: vector.ph:12; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]13; CHECK: vector.body:14; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]15; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i1616; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 1, [[DOTCAST]]17; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DST]], i16 [[OFFSET_IDX]]18; CHECK-NEXT: store <4 x i8> splat (i8 109), ptr [[TMP1]], align 119; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 420; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 99621; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]22; CHECK: middle.block:23; CHECK-NEXT: br label [[SCALAR_PH:%.*]]24; CHECK: scalar.ph:25; CHECK-NEXT: br label [[LOOP:%.*]]26; CHECK: loop:27; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 997, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]28; CHECK-NEXT: [[C:%.*]] = icmp ne i64 7304878031173690989, 029; CHECK-NEXT: [[C_EXT:%.*]] = zext i1 [[C]] to i6430; CHECK-NEXT: [[OR:%.*]] = or i64 7304878031173690989, [[C_EXT]]31; CHECK-NEXT: [[OR_TRUNC:%.*]] = trunc i64 [[OR]] to i832; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i16 [[IV]]33; CHECK-NEXT: store i8 [[OR_TRUNC]], ptr [[GEP]], align 134; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 135; CHECK-NEXT: [[EC:%.*]] = icmp eq i16 [[IV_NEXT]], 100036; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]37; CHECK: exit:38; CHECK-NEXT: ret i32 039;40entry:41 br label %loop42 43loop:44 %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ]45 %c = icmp ne i64 7304878031173690989, 046 %c.ext = zext i1 %c to i6447 %or = or i64 7304878031173690989, %c.ext48 %or.trunc = trunc i64 %or to i849 %gep = getelementptr i8, ptr %dst, i16 %iv50 store i8 %or.trunc, ptr %gep, align 151 %iv.next = add i16 %iv, 152 %ec = icmp eq i16 %iv.next, 100053 br i1 %ec, label %exit, label %loop54 55exit:56 ret i32 057}58 59 60define i32 @test_icmp_and_op_zext(ptr %dst, i64 %a) {61; CHECK-LABEL: define i32 @test_icmp_and_op_zext(62; CHECK-SAME: ptr [[DST:%.*]], i64 [[A:%.*]]) {63; CHECK-NEXT: entry:64; CHECK-NEXT: [[AND:%.*]] = and i64 [[A]], 730487803117369098965; CHECK-NEXT: br label [[VECTOR_PH:%.*]]66; CHECK: vector.ph:67; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[AND]], i64 068; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer69; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i64> [[BROADCAST_SPLAT]], zeroinitializer70; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i64>71; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[BROADCAST_SPLAT]], [[TMP2]]72; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i8>73; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]74; CHECK: vector.body:75; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]76; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i1677; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 1, [[DOTCAST]]78; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i16 [[OFFSET_IDX]]79; CHECK-NEXT: store <4 x i8> [[TMP4]], ptr [[TMP5]], align 180; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 481; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 99682; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]83; CHECK: middle.block:84; CHECK-NEXT: br label [[SCALAR_PH:%.*]]85; CHECK: scalar.ph:86; CHECK-NEXT: br label [[LOOP:%.*]]87; CHECK: loop:88; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 997, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]89; CHECK-NEXT: [[C:%.*]] = icmp ne i64 [[AND]], 090; CHECK-NEXT: [[C_EXT:%.*]] = zext i1 [[C]] to i6491; CHECK-NEXT: [[OR:%.*]] = or i64 [[AND]], [[C_EXT]]92; CHECK-NEXT: [[OR_TRUNC:%.*]] = trunc i64 [[OR]] to i893; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i16 [[IV]]94; CHECK-NEXT: store i8 [[OR_TRUNC]], ptr [[GEP]], align 195; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 196; CHECK-NEXT: [[EC:%.*]] = icmp eq i16 [[IV_NEXT]], 100097; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]98; CHECK: exit:99; CHECK-NEXT: ret i32 0100;101entry:102 %and = and i64 %a, 7304878031173690989103 br label %loop104 105loop:106 %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ]107 %c = icmp ne i64 %and, 0108 %c.ext = zext i1 %c to i64109 %or = or i64 %and, %c.ext110 %or.trunc = trunc i64 %or to i8111 %gep = getelementptr i8, ptr %dst, i16 %iv112 store i8 %or.trunc, ptr %gep, align 1113 %iv.next = add i16 %iv, 1114 %ec = icmp eq i16 %iv.next, 1000115 br i1 %ec, label %exit, label %loop116 117exit:118 ret i32 0119}120 121define void @ext_cmp(ptr %src.1, ptr %src.2, ptr noalias %dst) {122; CHECK-LABEL: define void @ext_cmp(123; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr noalias [[DST:%.*]]) {124; CHECK-NEXT: entry:125; CHECK-NEXT: br label [[VECTOR_PH:%.*]]126; CHECK: vector.ph:127; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]128; CHECK: vector.body:129; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]130; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX]]131; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP0]], align 2132; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4133; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000134; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]135; CHECK: middle.block:136; CHECK-NEXT: br label [[LOOP:%.*]]137; CHECK: exit:138; CHECK-NEXT: ret void139;140entry:141 br label %loop142 143loop:144 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]145 %gep.src.1 = getelementptr inbounds i16, ptr %src.1, i64 %iv146 %i2 = load i16, ptr %gep.src.1, align 2147 %i3 = sext i16 %i2 to i32148 %c.1 = icmp sgt i32 0, %i3149 %gep.src.2 = getelementptr inbounds i8, ptr %src.2, i64 %iv150 %i4 = load i8, ptr %gep.src.2, align 2151 %i5 = zext i8 %i4 to i32152 %i6 = select i1 %c.1, i32 0, i32 %i5153 %i7 = and i32 %i6, 0154 %i8 = trunc nuw nsw i32 %i7 to i16155 %gep.dst = getelementptr inbounds i16, ptr %dst, i64 %iv156 store i16 %i8, ptr %gep.dst, align 2157 %iv.next = add nsw i64 %iv, 1158 %ec = icmp eq i64 %iv.next, 1000159 br i1 %ec, label %exit, label %loop160 161exit:162 ret void163}164;.165; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}166; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}167; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}168; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}169; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}170; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}171; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}172;.173