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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 6define void @test_pr47927_lshr_const_shift_ops(ptr %dst, i32 %f) {7; CHECK-LABEL: define void @test_pr47927_lshr_const_shift_ops(8; CHECK-SAME: ptr [[DST:%.*]], i32 [[F:%.*]]) {9; CHECK-NEXT: entry:10; CHECK-NEXT: br label [[VECTOR_PH:%.*]]11; CHECK: vector.ph:12; CHECK-NEXT: [[TMP0:%.*]] = lshr i32 [[F]], 1813; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 014; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer15; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[BROADCAST_SPLAT]] to <4 x i8>16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]17; CHECK: vector.body:18; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]19; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i820; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[OFFSET_IDX]] to i6421; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP3]]22; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[TMP4]], align 823; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 424; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10025; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]26; CHECK: middle.block:27; CHECK-NEXT: br label [[LOOP:%.*]]28; CHECK: exit:29; CHECK-NEXT: ret void30;31entry:32 br label %loop33 34loop:35 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]36 %l = lshr i32 %f, 1837 %l.t = trunc i32 %l to i838 %iv.ext = zext i8 %iv to i6439 %gep = getelementptr inbounds i8, ptr %dst, i64 %iv.ext40 store i8 %l.t, ptr %gep, align 841 %iv.next = add i8 %iv, 142 %conv = zext i8 %iv.next to i3243 %c = icmp ne i32 %conv, 10044 br i1 %c, label %loop, label %exit45 46exit:47 ret void48}49 50define void @test_shl_const_shift_ops(ptr %dst, i32 %f) {51; CHECK-LABEL: define void @test_shl_const_shift_ops(52; CHECK-SAME: ptr [[DST:%.*]], i32 [[F:%.*]]) {53; CHECK-NEXT: entry:54; CHECK-NEXT: br label [[VECTOR_PH:%.*]]55; CHECK: vector.ph:56; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[F]], 1857; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 058; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer59; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[BROADCAST_SPLAT]] to <4 x i8>60; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]61; CHECK: vector.body:62; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]63; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i864; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[OFFSET_IDX]] to i6465; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP3]]66; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[TMP4]], align 867; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 468; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10069; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]70; CHECK: middle.block:71; CHECK-NEXT: br label [[LOOP:%.*]]72; CHECK: exit:73; CHECK-NEXT: ret void74;75entry:76 br label %loop77 78loop:79 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]80 %l = shl i32 %f, 1881 %l.t = trunc i32 %l to i882 %iv.ext = zext i8 %iv to i6483 %gep = getelementptr inbounds i8, ptr %dst, i64 %iv.ext84 store i8 %l.t, ptr %gep, align 885 %iv.next = add i8 %iv, 186 %conv = zext i8 %iv.next to i3287 %c = icmp ne i32 %conv, 10088 br i1 %c, label %loop, label %exit89 90exit:91 ret void92}93 94define void @test_ashr_const_shift_ops(ptr %dst, i32 %f) {95; CHECK-LABEL: define void @test_ashr_const_shift_ops(96; CHECK-SAME: ptr [[DST:%.*]], i32 [[F:%.*]]) {97; CHECK-NEXT: entry:98; CHECK-NEXT: br label [[VECTOR_PH:%.*]]99; CHECK: vector.ph:100; CHECK-NEXT: [[TMP0:%.*]] = ashr i32 [[F]], 18101; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0102; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer103; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[BROADCAST_SPLAT]] to <4 x i8>104; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]105; CHECK: vector.body:106; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]107; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8108; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[OFFSET_IDX]] to i64109; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP3]]110; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[TMP4]], align 8111; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4112; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100113; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]114; CHECK: middle.block:115; CHECK-NEXT: br label [[LOOP:%.*]]116; CHECK: exit:117; CHECK-NEXT: ret void118;119entry:120 br label %loop121 122loop:123 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]124 %l = ashr i32 %f, 18125 %l.t = trunc i32 %l to i8126 %iv.ext = zext i8 %iv to i64127 %gep = getelementptr inbounds i8, ptr %dst, i64 %iv.ext128 store i8 %l.t, ptr %gep, align 8129 %iv.next = add i8 %iv, 1130 %conv = zext i8 %iv.next to i32131 %c = icmp ne i32 %conv, 100132 br i1 %c, label %loop, label %exit133 134exit:135 ret void136}137 138define void @test_shl_const_shifted_op(ptr %dst, i32 %f) {139; CHECK-LABEL: define void @test_shl_const_shifted_op(140; CHECK-SAME: ptr [[DST:%.*]], i32 [[F:%.*]]) {141; CHECK-NEXT: entry:142; CHECK-NEXT: br label [[VECTOR_PH:%.*]]143; CHECK: vector.ph:144; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]145; CHECK: vector.body:146; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]147; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8148; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[OFFSET_IDX]] to i64149; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP1]]150; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1151; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>152; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i32> splat (i32 19), [[TMP4]]153; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[TMP5]] to <4 x i8>154; CHECK-NEXT: store <4 x i8> [[TMP6]], ptr [[TMP2]], align 8155; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4156; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100157; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]158; CHECK: middle.block:159; CHECK-NEXT: br label [[LOOP:%.*]]160; CHECK: exit:161; CHECK-NEXT: ret void162;163entry:164 br label %loop165 166loop:167 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]168 %iv.ext = zext i8 %iv to i64169 %gep = getelementptr inbounds i8, ptr %dst, i64 %iv.ext170 %lv = load i8, ptr %gep171 %zext = zext i8 %lv to i32172 %l = shl i32 19, %zext173 %l.t = trunc i32 %l to i8174 store i8 %l.t, ptr %gep, align 8175 %iv.next = add i8 %iv, 1176 %conv = zext i8 %iv.next to i32177 %c = icmp ne i32 %conv, 100178 br i1 %c, label %loop, label %exit179 180exit:181 ret void182}183 184 185define void @test_lshr_by_18(ptr %A) {186; CHECK-LABEL: define void @test_lshr_by_18(187; CHECK-SAME: ptr [[A:%.*]]) {188; CHECK-NEXT: entry:189; CHECK-NEXT: br label [[VECTOR_PH:%.*]]190; CHECK: vector.ph:191; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]192; CHECK: vector.body:193; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]194; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8195; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[OFFSET_IDX]] to i64196; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP1]]197; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1198; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>199; CHECK-NEXT: [[TMP5:%.*]] = lshr <4 x i32> [[TMP4]], splat (i32 18)200; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[TMP5]] to <4 x i8>201; CHECK-NEXT: store <4 x i8> [[TMP6]], ptr [[TMP2]], align 8202; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4203; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100204; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]205; CHECK: middle.block:206; CHECK-NEXT: br label [[LOOP:%.*]]207; CHECK: exit:208; CHECK-NEXT: ret void209;210entry:211 br label %loop212 213loop:214 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]215 %iv.ext = zext i8 %iv to i64216 %gep = getelementptr inbounds i8, ptr %A, i64 %iv.ext217 %lv = load i8, ptr %gep218 %lv.ext = zext i8 %lv to i32219 %l = lshr i32 %lv.ext, 18220 %l.t = trunc i32 %l to i8221 store i8 %l.t, ptr %gep, align 8222 %iv.next = add i8 %iv, 1223 %conv = zext i8 %iv.next to i32224 %c = icmp ne i32 %conv, 100225 br i1 %c, label %loop, label %exit226 227exit:228 ret void229}230 231define void @test_lshr_by_4(ptr %A) {232; CHECK-LABEL: define void @test_lshr_by_4(233; CHECK-SAME: ptr [[A:%.*]]) {234; CHECK-NEXT: entry:235; CHECK-NEXT: br label [[VECTOR_PH:%.*]]236; CHECK: vector.ph:237; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]238; CHECK: vector.body:239; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]240; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8241; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[OFFSET_IDX]] to i64242; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP1]]243; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1244; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i16>245; CHECK-NEXT: [[TMP5:%.*]] = lshr <4 x i16> [[TMP4]], splat (i16 4)246; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i16> [[TMP5]] to <4 x i8>247; CHECK-NEXT: store <4 x i8> [[TMP6]], ptr [[TMP2]], align 8248; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4249; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100250; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]251; CHECK: middle.block:252; CHECK-NEXT: br label [[LOOP:%.*]]253; CHECK: exit:254; CHECK-NEXT: ret void255;256entry:257 br label %loop258 259loop:260 %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]261 %iv.ext = zext i8 %iv to i64262 %gep = getelementptr inbounds i8, ptr %A, i64 %iv.ext263 %lv = load i8, ptr %gep264 %lv.ext = zext i8 %lv to i32265 %l = lshr i32 %lv.ext, 4266 %l.t = trunc i32 %l to i8267 store i8 %l.t, ptr %gep, align 8268 %iv.next = add i8 %iv, 1269 %conv = zext i8 %iv.next to i32270 %c = icmp ne i32 %conv, 100271 br i1 %c, label %loop, label %exit272 273exit:274 ret void275}276