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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s3 4@dst = external global [32 x i16], align 15 6define void @blend_uniform_iv_trunc(i1 %c) {7; CHECK-LABEL: define void @blend_uniform_iv_trunc(8; CHECK-SAME: i1 [[C:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: br label %[[VECTOR_PH:.*]]11; CHECK: [[VECTOR_PH]]:12; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]13; CHECK: [[VECTOR_BODY]]:14; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]15; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i1616; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C]], i16 [[TMP0]], i16 poison17; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 [[TMP6]]18; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP7]], align 219; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 420; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 3221; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]22; CHECK: [[MIDDLE_BLOCK]]:23; CHECK-NEXT: br label %[[EXIT:.*]]24; CHECK: [[EXIT]]:25; CHECK-NEXT: ret void26;27entry:28 br label %loop.header29 30loop.header: ; preds = %loop.latch, %entry31 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]32 %iv.trunc.2 = trunc i64 %iv to i1633 br i1 %c, label %loop.next, label %loop.latch34 35loop.next: ; preds = %loop.header36 br label %loop.latch37 38loop.latch: ; preds = %loop.next, %loop.header39 %blend = phi i16 [ poison, %loop.header ], [ %iv.trunc.2, %loop.next ]40 %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 %blend41 store i16 0, ptr %dst.ptr42 %iv.next = add nuw nsw i64 %iv, 143 %cmp439 = icmp ult i64 %iv, 3144 br i1 %cmp439, label %loop.header, label %exit45 46exit: ; preds = %loop.latch47 ret void48}49 50define void @blend_uniform_iv(i1 %c) {51; CHECK-LABEL: define void @blend_uniform_iv(52; CHECK-SAME: i1 [[C:%.*]]) {53; CHECK-NEXT: [[ENTRY:.*:]]54; CHECK-NEXT: br label %[[VECTOR_PH:.*]]55; CHECK: [[VECTOR_PH]]:56; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]57; CHECK: [[VECTOR_BODY]]:58; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]59; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C]], i64 [[INDEX]], i64 poison60; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP6]]61; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP7]], align 262; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 463; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 3264; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]65; CHECK: [[MIDDLE_BLOCK]]:66; CHECK-NEXT: br label %[[EXIT:.*]]67; CHECK: [[EXIT]]:68; CHECK-NEXT: ret void69;70 71entry:72 br label %loop.header73 74loop.header: ; preds = %loop.latch, %entry75 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]76 br i1 %c, label %loop.next, label %loop.latch77 78loop.next: ; preds = %loop.header79 br label %loop.latch80 81loop.latch: ; preds = %loop.next, %loop.header82 %blend = phi i64 [ poison, %loop.header ], [ %iv, %loop.next ]83 %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 %blend84 store i16 0, ptr %dst.ptr85 %iv.next = add nuw nsw i64 %iv, 186 %cmp439 = icmp ult i64 %iv, 3187 br i1 %cmp439, label %loop.header, label %exit88 89exit: ; preds = %loop.latch90 ret void91}92 93define void @blend_chain_iv(i1 %c) {94; CHECK-LABEL: define void @blend_chain_iv(95; CHECK-SAME: i1 [[C:%.*]]) {96; CHECK-NEXT: [[ENTRY:.*:]]97; CHECK-NEXT: br label %[[VECTOR_PH:.*]]98; CHECK: [[VECTOR_PH]]:99; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]100; CHECK: [[VECTOR_BODY]]:101; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]102; CHECK-NEXT: [[PREDPHI1:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]103; CHECK-NEXT: [[PREDPHI2:%.*]] = select i1 [[C]], <4 x i64> [[PREDPHI1]], <4 x i64> poison104; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 0105; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 1106; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 2107; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 3108; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP1]]109; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP3]]110; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP5]]111; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP7]]112; CHECK-NEXT: store i16 0, ptr [[TMP2]], align 2113; CHECK-NEXT: store i16 0, ptr [[TMP4]], align 2114; CHECK-NEXT: store i16 0, ptr [[TMP6]], align 2115; CHECK-NEXT: store i16 0, ptr [[TMP8]], align 2116; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4117; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[PREDPHI1]], splat (i64 4)118; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32119; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]120; CHECK: [[MIDDLE_BLOCK]]:121; CHECK-NEXT: br label %[[EXIT:.*]]122; CHECK: [[EXIT]]:123; CHECK-NEXT: ret void124;125 126entry:127 br label %loop.header128 129loop.header: ; preds = %loop.latch, %entry130 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]131 br i1 %c, label %loop.next, label %loop.latch132 133loop.next: ; preds = %loop.header134 br i1 %c, label %loop.next.2, label %loop.next.3135 136loop.next.2:137 br label %loop.next.3138 139loop.next.3:140 %blend.1 = phi i64 [ poison, %loop.next ], [ %iv, %loop.next.2 ]141 br label %loop.latch142 143loop.latch: ; preds = %loop.next, %loop.header144 %blend = phi i64 [ poison, %loop.header ], [ %blend.1, %loop.next.3 ]145 %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 %blend146 store i16 0, ptr %dst.ptr147 %iv.next = add nuw nsw i64 %iv, 1148 %cmp439 = icmp ult i64 %iv, 31149 br i1 %cmp439, label %loop.header, label %exit150 151exit: ; preds = %loop.latch152 ret void153}154 155define void @redundant_branch_and_blends_without_mask(ptr %A) {156; CHECK-LABEL: define void @redundant_branch_and_blends_without_mask(157; CHECK-SAME: ptr [[A:%.*]]) {158; CHECK-NEXT: [[ENTRY:.*:]]159; CHECK-NEXT: br label %[[VECTOR_PH:.*]]160; CHECK: [[VECTOR_PH]]:161; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]162; CHECK: [[VECTOR_BODY]]:163; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 0164; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 1165; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 2166; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 3167; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP5]], i32 0168; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x ptr> [[TMP35]], ptr [[TMP6]], i32 1169; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x ptr> [[TMP36]], ptr [[TMP7]], i32 2170; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x ptr> [[TMP37]], ptr [[TMP8]], i32 3171; CHECK-NEXT: br i1 true, label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]172; CHECK: [[PRED_LOAD_IF]]:173; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP5]], align 4174; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP10]], i32 0175; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]176; CHECK: [[PRED_LOAD_CONTINUE]]:177; CHECK-NEXT: [[TMP12:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP11]], %[[PRED_LOAD_IF]] ]178; CHECK-NEXT: br i1 true, label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]179; CHECK: [[PRED_LOAD_IF1]]:180; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP6]], align 4181; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP14]], i32 1182; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]183; CHECK: [[PRED_LOAD_CONTINUE2]]:184; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i32> [ [[TMP12]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]185; CHECK-NEXT: br i1 false, label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]186; CHECK: [[PRED_LOAD_IF3]]:187; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP7]], align 4188; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP18]], i32 2189; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]190; CHECK: [[PRED_LOAD_CONTINUE4]]:191; CHECK-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ [[TMP16]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP19]], %[[PRED_LOAD_IF3]] ]192; CHECK-NEXT: br i1 false, label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6:.*]]193; CHECK: [[PRED_LOAD_IF5]]:194; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP8]], align 4195; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[TMP22]], i32 3196; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE6]]197; CHECK: [[PRED_LOAD_CONTINUE6]]:198; CHECK-NEXT: [[TMP24:%.*]] = phi <4 x i32> [ [[TMP20]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP23]], %[[PRED_LOAD_IF5]] ]199; CHECK-NEXT: [[TMP25:%.*]] = add <4 x i32> [[TMP24]], splat (i32 10)200; CHECK-NEXT: [[TMP26:%.*]] = add <4 x i32> [[TMP24]], [[TMP25]]201; CHECK-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]202; CHECK: [[PRED_STORE_IF]]:203; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i32> [[TMP26]], i32 0204; CHECK-NEXT: store i32 [[TMP28]], ptr [[TMP5]], align 4205; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]206; CHECK: [[PRED_STORE_CONTINUE]]:207; CHECK-NEXT: br i1 true, label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]208; CHECK: [[PRED_STORE_IF7]]:209; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[TMP26]], i32 1210; CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP6]], align 4211; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]212; CHECK: [[PRED_STORE_CONTINUE8]]:213; CHECK-NEXT: br i1 false, label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]214; CHECK: [[PRED_STORE_IF9]]:215; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP26]], i32 2216; CHECK-NEXT: store i32 [[TMP32]], ptr [[TMP7]], align 4217; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]218; CHECK: [[PRED_STORE_CONTINUE10]]:219; CHECK-NEXT: br i1 false, label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]220; CHECK: [[PRED_STORE_IF11]]:221; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[TMP26]], i32 3222; CHECK-NEXT: store i32 [[TMP34]], ptr [[TMP8]], align 4223; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]224; CHECK: [[PRED_STORE_CONTINUE12]]:225; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]226; CHECK: [[MIDDLE_BLOCK]]:227; CHECK-NEXT: br label %[[EXIT:.*]]228; CHECK: [[EXIT]]:229; CHECK-NEXT: ret void230;231entry:232 br label %loop.header233 234loop.header:235 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]236 %gep.iv = getelementptr inbounds i32, ptr %A, i64 %iv237 %l = load i32, ptr %gep.iv238 %add = add i32 %l, 10239 br label %loop.latch240 241loop.latch:242 %p.1 = phi i32 [ %l, %loop.header ]243 %p.2 = phi i32 [ %add, %loop.header ]244 %res = add i32 %p.1, %p.2245 store i32 %res, ptr %gep.iv246 %iv.next = add i64 %iv, 1247 %ec = icmp eq i64 %iv, 1248 br i1 %ec, label %exit, label %loop.header249 250exit:251 ret void252}253 254;.255; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}256; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}257; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}258; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}259; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}260;.261