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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -p loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF8UF1 %s3; RUN: opt -p loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=VF8UF2 %s4; RUN: opt -p loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF16UF1 %s5 6; Check if the vector loop condition can be simplified to true for a given7; VF/IC combination.8define void @test_tc_between_8_and_17(ptr %A, i64 range(i64 8, 17) %N) {9; VF8UF1-LABEL: define void @test_tc_between_8_and_17(10; VF8UF1-SAME: ptr [[A:%.*]], i64 range(i64 8, 17) [[N:%.*]]) {11; VF8UF1-NEXT: [[ENTRY:.*:]]12; VF8UF1-NEXT: br label %[[VECTOR_PH:.*]]13; VF8UF1: [[VECTOR_PH]]:14; VF8UF1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 815; VF8UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]16; VF8UF1-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[N_VEC]]17; VF8UF1-NEXT: br label %[[VECTOR_BODY:.*]]18; VF8UF1: [[VECTOR_BODY]]:19; VF8UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]20; VF8UF1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]21; VF8UF1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[NEXT_GEP]], align 122; VF8UF1-NEXT: [[TMP2:%.*]] = add nsw <8 x i8> [[WIDE_LOAD]], splat (i8 10)23; VF8UF1-NEXT: store <8 x i8> [[TMP2]], ptr [[NEXT_GEP]], align 124; VF8UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 825; VF8UF1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]26; VF8UF1-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !prof [[PROF0:![0-9]+]], !llvm.loop [[LOOP1:![0-9]+]]27; VF8UF1: [[MIDDLE_BLOCK]]:28; VF8UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]29; VF8UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH:.*]], !prof [[PROF5:![0-9]+]]30; VF8UF1: [[SCALAR_PH]]:31; VF8UF1-NEXT: br label %[[LOOP:.*]]32; VF8UF1: [[LOOP]]:33; VF8UF1-NEXT: [[IV:%.*]] = phi i64 [ [[N_VEC]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]34; VF8UF1-NEXT: [[P_SRC:%.*]] = phi ptr [ [[TMP0]], %[[SCALAR_PH]] ], [ [[P_SRC_NEXT:%.*]], %[[LOOP]] ]35; VF8UF1-NEXT: [[P_SRC_NEXT]] = getelementptr inbounds i8, ptr [[P_SRC]], i64 136; VF8UF1-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 137; VF8UF1-NEXT: [[ADD:%.*]] = add nsw i8 [[L]], 1038; VF8UF1-NEXT: store i8 [[ADD]], ptr [[P_SRC]], align 139; VF8UF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 140; VF8UF1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]41; VF8UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !prof [[PROF6:![0-9]+]], !llvm.loop [[LOOP7:![0-9]+]]42; VF8UF1: [[EXIT]]:43; VF8UF1-NEXT: ret void44;45; VF8UF2-LABEL: define void @test_tc_between_8_and_17(46; VF8UF2-SAME: ptr [[A:%.*]], i64 range(i64 8, 17) [[N:%.*]]) {47; VF8UF2-NEXT: [[ENTRY:.*]]:48; VF8UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 1649; VF8UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]], !prof [[PROF0:![0-9]+]]50; VF8UF2: [[VECTOR_PH]]:51; VF8UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 1652; VF8UF2-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]53; VF8UF2-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[N_VEC]]54; VF8UF2-NEXT: br label %[[VECTOR_BODY:.*]]55; VF8UF2: [[VECTOR_BODY]]:56; VF8UF2-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[A]], i64 857; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[A]], align 158; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP2]], align 159; VF8UF2-NEXT: [[TMP3:%.*]] = add nsw <8 x i8> [[WIDE_LOAD]], splat (i8 10)60; VF8UF2-NEXT: [[TMP4:%.*]] = add nsw <8 x i8> [[WIDE_LOAD1]], splat (i8 10)61; VF8UF2-NEXT: store <8 x i8> [[TMP3]], ptr [[A]], align 162; VF8UF2-NEXT: store <8 x i8> [[TMP4]], ptr [[TMP2]], align 163; VF8UF2-NEXT: br label %[[MIDDLE_BLOCK:.*]]64; VF8UF2: [[MIDDLE_BLOCK]]:65; VF8UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]66; VF8UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]], !prof [[PROF1:![0-9]+]]67; VF8UF2: [[SCALAR_PH]]:68; VF8UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]69; VF8UF2-NEXT: [[BC_RESUME_VAL2:%.*]] = phi ptr [ [[TMP0]], %[[MIDDLE_BLOCK]] ], [ [[A]], %[[ENTRY]] ]70; VF8UF2-NEXT: br label %[[LOOP:.*]]71; VF8UF2: [[LOOP]]:72; VF8UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]73; VF8UF2-NEXT: [[P_SRC:%.*]] = phi ptr [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[P_SRC_NEXT:%.*]], %[[LOOP]] ]74; VF8UF2-NEXT: [[P_SRC_NEXT]] = getelementptr inbounds i8, ptr [[P_SRC]], i64 175; VF8UF2-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 176; VF8UF2-NEXT: [[ADD:%.*]] = add nsw i8 [[L]], 1077; VF8UF2-NEXT: store i8 [[ADD]], ptr [[P_SRC]], align 178; VF8UF2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 179; VF8UF2-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]80; VF8UF2-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !prof [[PROF2:![0-9]+]], !llvm.loop [[LOOP3:![0-9]+]]81; VF8UF2: [[EXIT]]:82; VF8UF2-NEXT: ret void83;84; VF16UF1-LABEL: define void @test_tc_between_8_and_17(85; VF16UF1-SAME: ptr [[A:%.*]], i64 range(i64 8, 17) [[N:%.*]]) {86; VF16UF1-NEXT: [[ENTRY:.*]]:87; VF16UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 1688; VF16UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]], !prof [[PROF0:![0-9]+]]89; VF16UF1: [[VECTOR_PH]]:90; VF16UF1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 1691; VF16UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]92; VF16UF1-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[A]], i64 [[N_VEC]]93; VF16UF1-NEXT: br label %[[VECTOR_BODY:.*]]94; VF16UF1: [[VECTOR_BODY]]:95; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[A]], align 196; VF16UF1-NEXT: [[TMP2:%.*]] = add nsw <16 x i8> [[WIDE_LOAD]], splat (i8 10)97; VF16UF1-NEXT: store <16 x i8> [[TMP2]], ptr [[A]], align 198; VF16UF1-NEXT: br label %[[MIDDLE_BLOCK:.*]]99; VF16UF1: [[MIDDLE_BLOCK]]:100; VF16UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]101; VF16UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]], !prof [[PROF1:![0-9]+]]102; VF16UF1: [[SCALAR_PH]]:103; VF16UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]104; VF16UF1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[TMP0]], %[[MIDDLE_BLOCK]] ], [ [[A]], %[[ENTRY]] ]105; VF16UF1-NEXT: br label %[[LOOP:.*]]106; VF16UF1: [[LOOP]]:107; VF16UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]108; VF16UF1-NEXT: [[P_SRC:%.*]] = phi ptr [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[P_SRC_NEXT:%.*]], %[[LOOP]] ]109; VF16UF1-NEXT: [[P_SRC_NEXT]] = getelementptr inbounds i8, ptr [[P_SRC]], i64 1110; VF16UF1-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 1111; VF16UF1-NEXT: [[ADD:%.*]] = add nsw i8 [[L]], 10112; VF16UF1-NEXT: store i8 [[ADD]], ptr [[P_SRC]], align 1113; VF16UF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1114; VF16UF1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]115; VF16UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !prof [[PROF2:![0-9]+]], !llvm.loop [[LOOP3:![0-9]+]]116; VF16UF1: [[EXIT]]:117; VF16UF1-NEXT: ret void118;119entry:120 br label %loop121 122loop:123 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]124 %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]125 %p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1126 %l = load i8, ptr %p.src, align 1127 %add = add nsw i8 %l, 10128 store i8 %add, ptr %p.src129 %iv.next = add nsw i64 %iv, 1130 %cmp = icmp eq i64 %iv.next, %N131 br i1 %cmp, label %exit, label %loop, !prof !0132 133exit:134 ret void135}136 137!0 = !{!"branch_weights", !"expected", i32 1, i32 2000}138