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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 52; RUN: opt -passes='loop-vectorize,verify<loops>' -force-vector-width=8 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF8UF1 %s3; RUN: opt -passes='loop-vectorize,verify<loops>' -force-vector-width=8 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=VF8UF2 %s4; RUN: opt -passes='loop-vectorize,verify<loops>' -force-vector-width=16 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=VF16UF1 %s5 6target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"7 8; Check if the vector loop condition can be simplified to true for a given9; VF/IC combination.10define i8 @test_early_exit_max_tc_less_than_16(ptr dereferenceable(16) %A) nosync nofree {11; VF8UF1-LABEL: define i8 @test_early_exit_max_tc_less_than_16(12; VF8UF1-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0:[0-9]+]] {13; VF8UF1-NEXT: [[ENTRY:.*:]]14; VF8UF1-NEXT: br label %[[VECTOR_PH:.*]]15; VF8UF1: [[VECTOR_PH]]:16; VF8UF1-NEXT: br label %[[VECTOR_BODY:.*]]17; VF8UF1: [[VECTOR_BODY]]:18; VF8UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]19; VF8UF1-NEXT: [[P_SRC:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]]20; VF8UF1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[P_SRC]], align 121; VF8UF1-NEXT: [[TMP3:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer22; VF8UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 823; VF8UF1-NEXT: [[TMP2:%.*]] = freeze <8 x i1> [[TMP3]]24; VF8UF1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP2]])25; VF8UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1626; VF8UF1-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]27; VF8UF1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]28; VF8UF1: [[MIDDLE_SPLIT]]:29; VF8UF1-NEXT: br i1 [[TMP4]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]30; VF8UF1: [[MIDDLE_BLOCK]]:31; VF8UF1-NEXT: br label %[[EXIT:.*]]32; VF8UF1: [[VECTOR_EARLY_EXIT]]:33; VF8UF1-NEXT: br label %[[EXIT]]34; VF8UF1: [[EXIT]]:35; VF8UF1-NEXT: [[RES:%.*]] = phi i8 [ 1, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]36; VF8UF1-NEXT: ret i8 [[RES]]37;38; VF8UF2-LABEL: define i8 @test_early_exit_max_tc_less_than_16(39; VF8UF2-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0:[0-9]+]] {40; VF8UF2-NEXT: [[ENTRY:.*:]]41; VF8UF2-NEXT: br label %[[VECTOR_PH:.*]]42; VF8UF2: [[VECTOR_PH]]:43; VF8UF2-NEXT: br label %[[VECTOR_BODY:.*]]44; VF8UF2: [[VECTOR_BODY]]:45; VF8UF2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 846; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[A]], align 147; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP0]], align 148; VF8UF2-NEXT: [[TMP1:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer49; VF8UF2-NEXT: [[TMP2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD1]], zeroinitializer50; VF8UF2-NEXT: [[TMP6:%.*]] = freeze <8 x i1> [[TMP1]]51; VF8UF2-NEXT: [[TMP5:%.*]] = freeze <8 x i1> [[TMP2]]52; VF8UF2-NEXT: [[TMP3:%.*]] = or <8 x i1> [[TMP6]], [[TMP5]]53; VF8UF2-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP3]])54; VF8UF2-NEXT: br label %[[MIDDLE_SPLIT:.*]]55; VF8UF2: [[MIDDLE_SPLIT]]:56; VF8UF2-NEXT: br i1 [[TMP4]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]57; VF8UF2: [[MIDDLE_BLOCK]]:58; VF8UF2-NEXT: br label %[[EXIT:.*]]59; VF8UF2: [[VECTOR_EARLY_EXIT]]:60; VF8UF2-NEXT: br label %[[EXIT]]61; VF8UF2: [[EXIT]]:62; VF8UF2-NEXT: [[RES:%.*]] = phi i8 [ 1, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]63; VF8UF2-NEXT: ret i8 [[RES]]64;65; VF16UF1-LABEL: define i8 @test_early_exit_max_tc_less_than_16(66; VF16UF1-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0:[0-9]+]] {67; VF16UF1-NEXT: [[ENTRY:.*:]]68; VF16UF1-NEXT: br label %[[VECTOR_PH:.*]]69; VF16UF1: [[VECTOR_PH]]:70; VF16UF1-NEXT: br label %[[VECTOR_BODY:.*]]71; VF16UF1: [[VECTOR_BODY]]:72; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[A]], align 173; VF16UF1-NEXT: [[TMP3:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer74; VF16UF1-NEXT: [[TMP1:%.*]] = freeze <16 x i1> [[TMP3]]75; VF16UF1-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])76; VF16UF1-NEXT: br label %[[MIDDLE_SPLIT:.*]]77; VF16UF1: [[MIDDLE_SPLIT]]:78; VF16UF1-NEXT: br i1 [[TMP2]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]79; VF16UF1: [[MIDDLE_BLOCK]]:80; VF16UF1-NEXT: br label %[[EXIT:.*]]81; VF16UF1: [[VECTOR_EARLY_EXIT]]:82; VF16UF1-NEXT: br label %[[EXIT]]83; VF16UF1: [[EXIT]]:84; VF16UF1-NEXT: [[RES:%.*]] = phi i8 [ 1, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]85; VF16UF1-NEXT: ret i8 [[RES]]86;87entry:88 br label %loop.header89 90loop.header:91 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]92 %p.src = getelementptr inbounds i8, ptr %A, i64 %iv93 %l = load i8, ptr %p.src, align 194 %c = icmp eq i8 %l, 095 br i1 %c, label %exit, label %loop.latch96 97loop.latch:98 %iv.next = add nsw i64 %iv, 199 %cmp = icmp eq i64 %iv.next, 16100 br i1 %cmp, label %exit, label %loop.header101 102exit:103 %res = phi i8 [ 0, %loop.header ], [ 1, %loop.latch ]104 ret i8 %res105}106 107define i64 @test_early_exit_max_tc_less_than_16_with_iv_used_outside(ptr dereferenceable(16) %A) nosync nofree {108; VF8UF1-LABEL: define i64 @test_early_exit_max_tc_less_than_16_with_iv_used_outside(109; VF8UF1-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0]] {110; VF8UF1-NEXT: [[ENTRY:.*:]]111; VF8UF1-NEXT: br label %[[VECTOR_PH:.*]]112; VF8UF1: [[VECTOR_PH]]:113; VF8UF1-NEXT: br label %[[VECTOR_BODY:.*]]114; VF8UF1: [[VECTOR_BODY]]:115; VF8UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]116; VF8UF1-NEXT: [[P_SRC:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]]117; VF8UF1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[P_SRC]], align 1118; VF8UF1-NEXT: [[TMP3:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer119; VF8UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8120; VF8UF1-NEXT: [[TMP2:%.*]] = freeze <8 x i1> [[TMP3]]121; VF8UF1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP2]])122; VF8UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16123; VF8UF1-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]124; VF8UF1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]125; VF8UF1: [[MIDDLE_SPLIT]]:126; VF8UF1-NEXT: br i1 [[TMP4]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]127; VF8UF1: [[MIDDLE_BLOCK]]:128; VF8UF1-NEXT: br label %[[EXIT:.*]]129; VF8UF1: [[VECTOR_EARLY_EXIT]]:130; VF8UF1-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> [[TMP3]], i1 false)131; VF8UF1-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], [[FIRST_ACTIVE_LANE]]132; VF8UF1-NEXT: br label %[[EXIT]]133; VF8UF1: [[EXIT]]:134; VF8UF1-NEXT: [[RES:%.*]] = phi i64 [ 1, %[[MIDDLE_BLOCK]] ], [ [[TMP8]], %[[VECTOR_EARLY_EXIT]] ]135; VF8UF1-NEXT: ret i64 [[RES]]136;137; VF8UF2-LABEL: define i64 @test_early_exit_max_tc_less_than_16_with_iv_used_outside(138; VF8UF2-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0]] {139; VF8UF2-NEXT: [[ENTRY:.*:]]140; VF8UF2-NEXT: br label %[[VECTOR_PH:.*]]141; VF8UF2: [[VECTOR_PH]]:142; VF8UF2-NEXT: br label %[[VECTOR_BODY:.*]]143; VF8UF2: [[VECTOR_BODY]]:144; VF8UF2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 8145; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[A]], align 1146; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1147; VF8UF2-NEXT: [[TMP1:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer148; VF8UF2-NEXT: [[TMP2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD1]], zeroinitializer149; VF8UF2-NEXT: [[TMP13:%.*]] = freeze <8 x i1> [[TMP1]]150; VF8UF2-NEXT: [[TMP6:%.*]] = freeze <8 x i1> [[TMP2]]151; VF8UF2-NEXT: [[TMP3:%.*]] = or <8 x i1> [[TMP13]], [[TMP6]]152; VF8UF2-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP3]])153; VF8UF2-NEXT: br label %[[MIDDLE_SPLIT:.*]]154; VF8UF2: [[MIDDLE_SPLIT]]:155; VF8UF2-NEXT: br i1 [[TMP4]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]156; VF8UF2: [[MIDDLE_BLOCK]]:157; VF8UF2-NEXT: br label %[[EXIT:.*]]158; VF8UF2: [[VECTOR_EARLY_EXIT]]:159; VF8UF2-NEXT: [[TMP5:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> [[TMP2]], i1 false)160; VF8UF2-NEXT: [[TMP7:%.*]] = add i64 8, [[TMP5]]161; VF8UF2-NEXT: [[TMP8:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> [[TMP1]], i1 false)162; VF8UF2-NEXT: [[TMP9:%.*]] = add i64 0, [[TMP8]]163; VF8UF2-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP8]], 8164; VF8UF2-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 [[TMP7]]165; VF8UF2-NEXT: br label %[[EXIT]]166; VF8UF2: [[EXIT]]:167; VF8UF2-NEXT: [[RES:%.*]] = phi i64 [ 1, %[[MIDDLE_BLOCK]] ], [ [[TMP11]], %[[VECTOR_EARLY_EXIT]] ]168; VF8UF2-NEXT: ret i64 [[RES]]169;170; VF16UF1-LABEL: define i64 @test_early_exit_max_tc_less_than_16_with_iv_used_outside(171; VF16UF1-SAME: ptr dereferenceable(16) [[A:%.*]]) #[[ATTR0]] {172; VF16UF1-NEXT: [[ENTRY:.*:]]173; VF16UF1-NEXT: br label %[[VECTOR_PH:.*]]174; VF16UF1: [[VECTOR_PH]]:175; VF16UF1-NEXT: br label %[[VECTOR_BODY:.*]]176; VF16UF1: [[VECTOR_BODY]]:177; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[A]], align 1178; VF16UF1-NEXT: [[TMP3:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer179; VF16UF1-NEXT: [[TMP1:%.*]] = freeze <16 x i1> [[TMP3]]180; VF16UF1-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])181; VF16UF1-NEXT: br label %[[MIDDLE_SPLIT:.*]]182; VF16UF1: [[MIDDLE_SPLIT]]:183; VF16UF1-NEXT: br i1 [[TMP2]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]184; VF16UF1: [[MIDDLE_BLOCK]]:185; VF16UF1-NEXT: br label %[[EXIT:.*]]186; VF16UF1: [[VECTOR_EARLY_EXIT]]:187; VF16UF1-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> [[TMP3]], i1 false)188; VF16UF1-NEXT: br label %[[EXIT]]189; VF16UF1: [[EXIT]]:190; VF16UF1-NEXT: [[RES:%.*]] = phi i64 [ 1, %[[MIDDLE_BLOCK]] ], [ [[FIRST_ACTIVE_LANE]], %[[VECTOR_EARLY_EXIT]] ]191; VF16UF1-NEXT: ret i64 [[RES]]192;193entry:194 br label %loop.header195 196loop.header:197 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]198 %p.src = getelementptr inbounds i8, ptr %A, i64 %iv199 %l = load i8, ptr %p.src, align 1200 %c = icmp eq i8 %l, 0201 br i1 %c, label %exit, label %loop.latch202 203loop.latch:204 %iv.next = add nsw i64 %iv, 1205 %cmp = icmp eq i64 %iv.next, 16206 br i1 %cmp, label %exit, label %loop.header207 208exit:209 %res = phi i64 [ %iv, %loop.header ], [ 1, %loop.latch ]210 ret i64 %res211}212 213define i8 @test_early_exit_max_vector_tc_eq_16(ptr dereferenceable(17) %A) nosync nofree {214; VF8UF1-LABEL: define i8 @test_early_exit_max_vector_tc_eq_16(215; VF8UF1-SAME: ptr dereferenceable(17) [[A:%.*]]) #[[ATTR0]] {216; VF8UF1-NEXT: [[ENTRY:.*:]]217; VF8UF1-NEXT: br label %[[VECTOR_PH:.*]]218; VF8UF1: [[VECTOR_PH]]:219; VF8UF1-NEXT: br label %[[VECTOR_BODY:.*]]220; VF8UF1: [[VECTOR_BODY]]:221; VF8UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]222; VF8UF1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]]223; VF8UF1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1224; VF8UF1-NEXT: [[TMP1:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer225; VF8UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8226; VF8UF1-NEXT: [[TMP5:%.*]] = freeze <8 x i1> [[TMP1]]227; VF8UF1-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP5]])228; VF8UF1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16229; VF8UF1-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]230; VF8UF1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]231; VF8UF1: [[MIDDLE_SPLIT]]:232; VF8UF1-NEXT: br i1 [[TMP2]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]233; VF8UF1: [[MIDDLE_BLOCK]]:234; VF8UF1-NEXT: br label %[[SCALAR_PH:.*]]235; VF8UF1: [[VECTOR_EARLY_EXIT]]:236; VF8UF1-NEXT: br label %[[EXIT:.*]]237; VF8UF1: [[SCALAR_PH]]:238; VF8UF1-NEXT: br label %[[LOOP_HEADER:.*]]239; VF8UF1: [[LOOP_HEADER]]:240; VF8UF1-NEXT: [[IV:%.*]] = phi i64 [ 16, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]241; VF8UF1-NEXT: [[P_SRC:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IV]]242; VF8UF1-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 1243; VF8UF1-NEXT: [[C:%.*]] = icmp eq i8 [[L]], 0244; VF8UF1-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP_LATCH]]245; VF8UF1: [[LOOP_LATCH]]:246; VF8UF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1247; VF8UF1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 17248; VF8UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]249; VF8UF1: [[EXIT]]:250; VF8UF1-NEXT: [[RES:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ 1, %[[LOOP_LATCH]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]251; VF8UF1-NEXT: ret i8 [[RES]]252;253; VF8UF2-LABEL: define i8 @test_early_exit_max_vector_tc_eq_16(254; VF8UF2-SAME: ptr dereferenceable(17) [[A:%.*]]) #[[ATTR0]] {255; VF8UF2-NEXT: [[ENTRY:.*:]]256; VF8UF2-NEXT: br label %[[VECTOR_PH:.*]]257; VF8UF2: [[VECTOR_PH]]:258; VF8UF2-NEXT: br label %[[VECTOR_BODY:.*]]259; VF8UF2: [[VECTOR_BODY]]:260; VF8UF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 8261; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[A]], align 1262; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP1]], align 1263; VF8UF2-NEXT: [[TMP2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer264; VF8UF2-NEXT: [[TMP3:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD1]], zeroinitializer265; VF8UF2-NEXT: [[TMP7:%.*]] = freeze <8 x i1> [[TMP2]]266; VF8UF2-NEXT: [[TMP6:%.*]] = freeze <8 x i1> [[TMP3]]267; VF8UF2-NEXT: [[TMP4:%.*]] = or <8 x i1> [[TMP7]], [[TMP6]]268; VF8UF2-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP4]])269; VF8UF2-NEXT: br label %[[MIDDLE_SPLIT:.*]]270; VF8UF2: [[MIDDLE_SPLIT]]:271; VF8UF2-NEXT: br i1 [[TMP5]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]272; VF8UF2: [[MIDDLE_BLOCK]]:273; VF8UF2-NEXT: br label %[[SCALAR_PH:.*]]274; VF8UF2: [[VECTOR_EARLY_EXIT]]:275; VF8UF2-NEXT: br label %[[EXIT:.*]]276; VF8UF2: [[SCALAR_PH]]:277; VF8UF2-NEXT: br label %[[LOOP_HEADER:.*]]278; VF8UF2: [[LOOP_HEADER]]:279; VF8UF2-NEXT: [[IV:%.*]] = phi i64 [ 16, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]280; VF8UF2-NEXT: [[P_SRC:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IV]]281; VF8UF2-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 1282; VF8UF2-NEXT: [[C:%.*]] = icmp eq i8 [[L]], 0283; VF8UF2-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP_LATCH]]284; VF8UF2: [[LOOP_LATCH]]:285; VF8UF2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1286; VF8UF2-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 17287; VF8UF2-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP0:![0-9]+]]288; VF8UF2: [[EXIT]]:289; VF8UF2-NEXT: [[RES:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ 1, %[[LOOP_LATCH]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]290; VF8UF2-NEXT: ret i8 [[RES]]291;292; VF16UF1-LABEL: define i8 @test_early_exit_max_vector_tc_eq_16(293; VF16UF1-SAME: ptr dereferenceable(17) [[A:%.*]]) #[[ATTR0]] {294; VF16UF1-NEXT: [[ENTRY:.*:]]295; VF16UF1-NEXT: br label %[[VECTOR_PH:.*]]296; VF16UF1: [[VECTOR_PH]]:297; VF16UF1-NEXT: br label %[[VECTOR_BODY:.*]]298; VF16UF1: [[VECTOR_BODY]]:299; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[A]], align 1300; VF16UF1-NEXT: [[TMP1:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer301; VF16UF1-NEXT: [[TMP3:%.*]] = freeze <16 x i1> [[TMP1]]302; VF16UF1-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])303; VF16UF1-NEXT: br label %[[MIDDLE_SPLIT:.*]]304; VF16UF1: [[MIDDLE_SPLIT]]:305; VF16UF1-NEXT: br i1 [[TMP2]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]306; VF16UF1: [[MIDDLE_BLOCK]]:307; VF16UF1-NEXT: br label %[[SCALAR_PH:.*]]308; VF16UF1: [[VECTOR_EARLY_EXIT]]:309; VF16UF1-NEXT: br label %[[EXIT:.*]]310; VF16UF1: [[SCALAR_PH]]:311; VF16UF1-NEXT: br label %[[LOOP_HEADER:.*]]312; VF16UF1: [[LOOP_HEADER]]:313; VF16UF1-NEXT: [[IV:%.*]] = phi i64 [ 16, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]314; VF16UF1-NEXT: [[P_SRC:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IV]]315; VF16UF1-NEXT: [[L:%.*]] = load i8, ptr [[P_SRC]], align 1316; VF16UF1-NEXT: [[C:%.*]] = icmp eq i8 [[L]], 0317; VF16UF1-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP_LATCH]]318; VF16UF1: [[LOOP_LATCH]]:319; VF16UF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1320; VF16UF1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 17321; VF16UF1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP0:![0-9]+]]322; VF16UF1: [[EXIT]]:323; VF16UF1-NEXT: [[RES:%.*]] = phi i8 [ 0, %[[LOOP_HEADER]] ], [ 1, %[[LOOP_LATCH]] ], [ 0, %[[VECTOR_EARLY_EXIT]] ]324; VF16UF1-NEXT: ret i8 [[RES]]325;326entry:327 br label %loop.header328 329loop.header:330 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]331 %p.src = getelementptr inbounds i8, ptr %A, i64 %iv332 %l = load i8, ptr %p.src, align 1333 %c = icmp eq i8 %l, 0334 br i1 %c, label %exit, label %loop.latch335 336loop.latch:337 %iv.next = add nsw i64 %iv, 1338 %cmp = icmp eq i64 %iv.next, 17339 br i1 %cmp, label %exit, label %loop.header340 341exit:342 %res = phi i8 [ 0, %loop.header ], [ 1, %loop.latch ]343 ret i8 %res344}345 346 347