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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s3 4; This test used to crash due to missing Or/Not cases in inferScalarTypeForRecipe.5define void @vplan_incomplete_cases_tc2(i8 %x, i8 %y) {6; CHECK-LABEL: define void @vplan_incomplete_cases_tc2(7; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {8; CHECK-NEXT: [[ENTRY:.*]]:9; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]10; CHECK: [[LOOP_HEADER]]:11; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[ENTRY]] ]12; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[Y]]13; CHECK-NEXT: [[EXTRACT_T:%.*]] = trunc i8 [[AND]] to i114; CHECK-NEXT: br i1 [[EXTRACT_T]], label %[[LATCH]], label %[[INDIRECT_LATCH:.*]]15; CHECK: [[INDIRECT_LATCH]]:16; CHECK-NEXT: br label %[[LATCH]]17; CHECK: [[LATCH]]:18; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 119; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[IV]] to i3220; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ZEXT]], 121; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]22; CHECK: [[EXIT]]:23; CHECK-NEXT: ret void24;25entry:26 br label %loop.header27 28loop.header: ; preds = %latch, %entry29 %iv = phi i8 [ %iv.next, %latch ], [ 0, %entry ]30 %and = and i8 %x, %y31 %extract.t = trunc i8 %and to i132 br i1 %extract.t, label %latch, label %indirect.latch33 34indirect.latch: ; preds = %loop.header35 br label %latch36 37latch: ; preds = %indirect.latch, loop.header38 %iv.next = add i8 %iv, 139 %zext = zext i8 %iv to i3240 %cmp = icmp ult i32 %zext, 141 br i1 %cmp, label %loop.header, label %exit42 43exit: ; preds = %latch44 ret void45}46 47; This test used to crash due to missing the LogicalAnd case in inferScalarTypeForRecipe.48define void @vplan_incomplete_cases_tc3(i8 %x, i8 %y) {49; CHECK-LABEL: define void @vplan_incomplete_cases_tc3(50; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {51; CHECK-NEXT: [[ENTRY:.*]]:52; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]53; CHECK: [[LOOP_HEADER]]:54; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[ENTRY]] ]55; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[Y]]56; CHECK-NEXT: [[EXTRACT_T:%.*]] = trunc i8 [[AND]] to i157; CHECK-NEXT: br i1 [[EXTRACT_T]], label %[[LATCH]], label %[[INDIRECT_LATCH:.*]]58; CHECK: [[INDIRECT_LATCH]]:59; CHECK-NEXT: br label %[[LATCH]]60; CHECK: [[LATCH]]:61; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 162; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[IV]] to i3263; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ZEXT]], 264; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]65; CHECK: [[EXIT]]:66; CHECK-NEXT: ret void67;68entry:69 br label %loop.header70 71loop.header: ; preds = %latch, %entry72 %iv = phi i8 [ %iv.next, %latch ], [ 0, %entry ]73 %and = and i8 %x, %y74 %extract.t = trunc i8 %and to i175 br i1 %extract.t, label %latch, label %indirect.latch76 77indirect.latch: ; preds = %loop.header78 br label %latch79 80latch: ; preds = %indirect.latch, loop.header81 %iv.next = add i8 %iv, 182 %zext = zext i8 %iv to i3283 %cmp = icmp ult i32 %zext, 284 br i1 %cmp, label %loop.header, label %exit85 86exit: ; preds = %latch87 ret void88}89