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1; REQUIRES: asserts2 3; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s4 5; Tests for printing VPlans with reductions.6 7define float @print_reduction(i64 %n, ptr noalias %y) {8; CHECK-LABEL: Checking a loop in 'print_reduction'9; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {10; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF11; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF12; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count13; CHECK-NEXT: Live-in ir<%n> = original trip-count14; CHECK-EMPTY:15; CHECK-NEXT: ir-bb<entry>:16; CHECK-NEXT: Successor(s): scalar.ph, vector.ph17; CHECK-EMPTY:18; CHECK-NEXT: vector.ph:19; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1>20; CHECK-NEXT: Successor(s): vector loop21; CHECK-EMPTY:22; CHECK-NEXT: <x1> vector loop: {23; CHECK-NEXT: vector.body:24; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>25; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[RDX_START]]>, ir<%red.next>26; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>27; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[STEPS]]>28; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx>29; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]>30; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>)31; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>32; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>33; CHECK-NEXT: No successors34; CHECK-NEXT: }35; CHECK-NEXT: Successor(s): middle.block36; CHECK-EMPTY:37; CHECK-NEXT: middle.block:38; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result fast ir<%red>, ir<%red.next>39; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]>40; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>41; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph42; CHECK-EMPTY:43; CHECK-NEXT: ir-bb<exit>44; CHECK-NEXT: IR %red.next.lcssa = phi float [ %red.next, %loop ] (extra operand: vp<[[RED_RES]]> from middle.block)45; CHECK-NEXT: No successors46; CHECK-EMPTY:47; CHECK-NEXT: scalar.ph48; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]49; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb<entry> ]50; CHECK-NEXT: Successor(s): ir-bb<loop>51; CHECK-EMPTY:52; CHECK-NEXT: ir-bb<loop>:53; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph)54; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n55; CHECK-NEXT: No successors56; CHECK-NEXT: }57;58entry:59 br label %loop60 61loop: ; preds = %entry, %loop62 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]63 %red = phi float [ %red.next, %loop ], [ 0.0, %entry ]64 %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv65 %lv = load float, ptr %arrayidx, align 466 %red.next = fadd fast float %lv, %red67 %iv.next = add i64 %iv, 168 %exitcond = icmp eq i64 %iv.next, %n69 br i1 %exitcond, label %exit, label %loop70 71exit: ; preds = %loop, %entry72 ret float %red.next73}74 75define void @print_reduction_with_invariant_store(i64 %n, ptr noalias %y, ptr noalias %dst) {76; CHECK-LABEL: Checking a loop in 'print_reduction_with_invariant_store'77; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {78; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF79; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF80; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count81; CHECK-NEXT: Live-in ir<%n> = original trip-count82; CHECK-EMPTY:83; CHECK-NEXT: ir-bb<entry>:84; CHECK-NEXT: Successor(s): scalar.ph, vector.ph85; CHECK-EMPTY:86; CHECK-NEXT: vector.ph:87; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1>88; CHECK-NEXT: Successor(s): vector loop89; CHECK-EMPTY:90; CHECK-NEXT: <x1> vector loop: {91; CHECK-NEXT: vector.body:92; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>93; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[RDX_START]]>, ir<%red.next>94; CHECK-NEXT: vp<[[IV:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>95; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[IV]]>96; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx>97; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]>98; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>)99; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>100; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>101; CHECK-NEXT: No successors102; CHECK-NEXT: }103; CHECK-NEXT: Successor(s): middle.block104; CHECK-EMPTY:105; CHECK-NEXT: middle.block:106; CHECK-NEXT: EMIT vp<[[RED_RES:.+]]> = compute-reduction-result fast ir<%red>, ir<%red.next>107; CHECK-NEXT: CLONE store vp<[[RED_RES]]>, ir<%dst>108; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]>109; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>110; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph111; CHECK-EMPTY:112; CHECK-NEXT: ir-bb<exit>113; CHECK-NEXT: No successors114; CHECK-EMPTY:115; CHECK-NEXT: scalar.ph116; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]117; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb<entry> ]118; CHECK-NEXT: Successor(s): ir-bb<loop>119; CHECK-EMPTY:120; CHECK-NEXT: ir-bb<loop>:121; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph)122; CHECK-NEXT: IR %red = phi float [ %red.next, %loop ], [ 0.000000e+00, %entry ]123; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n124; CHECK-NEXT: No successors125; CHECK-NEXT: }126;127entry:128 br label %loop129 130loop: ; preds = %entry, %loop131 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]132 %red = phi float [ %red.next, %loop ], [ 0.0, %entry ]133 %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv134 %lv = load float, ptr %arrayidx, align 4135 %red.next = fadd fast float %lv, %red136 store float %red.next, ptr %dst, align 4137 %iv.next = add i64 %iv, 1138 %exitcond = icmp eq i64 %iv.next, %n139 br i1 %exitcond, label %exit, label %loop140 141exit: ; preds = %loop, %entry142 ret void143}144 145define float @print_fmuladd_strict(ptr %a, ptr %b, i64 %n) {146; CHECK-LABEL: Checking a loop in 'print_fmuladd_strict'147; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {148; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF149; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF150; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count151; CHECK-NEXT: Live-in ir<%n> = original trip-count152; CHECK-EMPTY:153; CHECK-NEXT: ir-bb<entry>:154; CHECK-NEXT: Successor(s): scalar.ph, vector.ph155; CHECK-EMPTY:156; CHECK-NEXT: vector.ph:157; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector nnan ninf nsz ir<0.000000e+00>, ir<0.000000e+00>, ir<1>158; CHECK-NEXT: Successor(s): vector loop159; CHECK-EMPTY:160; CHECK-NEXT: <x1> vector loop: {161; CHECK-NEXT: vector.body:162; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>163; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%sum.07> = phi vp<[[RDX_START]]>, ir<%muladd>164; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>165; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>166; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx>167; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VEC_PTR]]>168; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%b>, vp<[[STEPS]]>169; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%arrayidx2>170; CHECK-NEXT: WIDEN ir<%l.b> = load vp<[[VEC_PTR2]]>171; CHECK-NEXT: EMIT vp<[[FMUL:%.+]]> = fmul nnan ninf nsz ir<%l.a>, ir<%l.b>172; CHECK-NEXT: REDUCE ir<[[MULADD:%.+]]> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<[[FMUL]]>)173; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>174; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>175; CHECK-NEXT: No successors176; CHECK-NEXT: }177; CHECK-NEXT: Successor(s): middle.block178; CHECK-EMPTY:179; CHECK-NEXT: middle.block:180; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result nnan ninf nsz ir<%sum.07>, ir<[[MULADD]]>181; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]>182; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>183; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph184; CHECK-EMPTY:185; CHECK-NEXT: ir-bb<exit>186; CHECK-NEXT: IR %muladd.lcssa = phi float [ %muladd, %loop ] (extra operand: vp<[[RED_RES]]> from middle.block)187; CHECK-NEXT: No successors188; CHECK-EMPTY:189; CHECK-NEXT: scalar.ph190; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]191; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb<entry> ]192; CHECK-NEXT: Successor(s): ir-bb<loop>193; CHECK-EMPTY:194; CHECK-NEXT: ir-bb<loop>:195; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph)196; CHECK-NEXT: IR %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %loop ] (extra operand: vp<[[RED_RESUME]]> from scalar.ph)197; CHECK: IR %exitcond.not = icmp eq i64 %iv.next, %n198; CHECK-NEXT: No successors199; CHECK-NEXT:}200 201entry:202 br label %loop203 204loop:205 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]206 %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %loop ]207 %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv208 %l.a = load float, ptr %arrayidx, align 4209 %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv210 %l.b = load float, ptr %arrayidx2, align 4211 %muladd = tail call nnan ninf nsz float @llvm.fmuladd.f32(float %l.a, float %l.b, float %sum.07)212 %iv.next = add nuw nsw i64 %iv, 1213 %exitcond.not = icmp eq i64 %iv.next, %n214 br i1 %exitcond.not, label %exit, label %loop215 216exit:217 ret float %muladd218}219 220define i64 @find_last_iv(ptr %a, i64 %n, i64 %start) {221; CHECK-LABEL: Checking a loop in 'find_last_iv'222; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {223; CHECK: <x1> vector loop: {224; CHECK-NEXT: vector.body:225; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next>226; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<{{.+}}>227; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi ir<-9223372036854775808>, ir<%cond>228; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>229; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr inbounds ir<%a>, vp<[[SCALAR_STEPS]]>230; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.a>231; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VEC_PTR]]>232; CHECK-NEXT: WIDEN ir<%cmp2> = icmp eq ir<%l.a>, ir<%start>233; CHECK-NEXT: WIDEN-SELECT ir<%cond> = select ir<%cmp2>, ir<%iv>, ir<%rdx>234; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[CAN_IV]]>, vp<{{.+}}>235; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<{{.+}}>236; CHECK-NEXT: No successors237; CHECK-NEXT: }238; CHECK-NEXT: Successor(s): middle.block239; CHECK-EMPTY:240; CHECK-NEXT: middle.block:241; CHECK-NEXT: EMIT vp<[[RDX_RES:%.+]]> = compute-find-iv-result ir<%rdx>, ir<%start>, ir<-9223372036854775808>, ir<%cond>242; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<{{.+}}>243; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>244; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph245; CHECK-EMPTY:246; CHECK: ir-bb<exit>:247; CHECK-NEXT: IR %cond.lcssa = phi i64 [ %cond, %loop ] (extra operand: vp<[[RDX_RES]]> from middle.block)248; CHECK-NEXT: No successors249; CHECK-EMPTY:250; CHECK-NEXT: scalar.ph:251; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<{{.+}}>, middle.block ], [ ir<0>, ir-bb<entry> ]252; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[RDX_RES]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]253;254entry:255 br label %loop256 257loop:258 %iv = phi i64 [ 0, %entry ], [ %inc, %loop ]259 %rdx = phi i64 [ %start, %entry ], [ %cond, %loop ]260 %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv261 %l.a = load i64, ptr %gep.a, align 8262 %cmp2 = icmp eq i64 %l.a, %start263 %cond = select i1 %cmp2, i64 %iv, i64 %rdx264 %inc = add nuw nsw i64 %iv, 1265 %exitcond.not = icmp eq i64 %inc, %n266 br i1 %exitcond.not, label %exit, label %loop267 268exit:269 ret i64 %cond270}271 272define i64 @print_extended_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {273; CHECK-LABEL: 'print_extended_reduction'274; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {275; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF276; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF277; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count278; CHECK-NEXT: Live-in ir<%n> = original trip-count279; CHECK-EMPTY:280; CHECK: vector.ph:281; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>282; CHECK-NEXT: Successor(s): vector loop283; CHECK-EMPTY:284; CHECK-NEXT: <x1> vector loop: {285; CHECK-NEXT: vector.body:286; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>287; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>288; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>289; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>290; CHECK-NEXT: vp<[[ADDR:%.+]]> = vector-pointer inbounds ir<%arrayidx>291; CHECK-NEXT: WIDEN ir<[[LOAD:%.+]]> = load vp<[[ADDR]]>292; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (ir<[[LOAD]]> zext to i64)293; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>294; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>295; CHECK-NEXT: No successors296; CHECK-NEXT: }297;298entry:299 br label %loop300 301loop:302 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]303 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]304 %arrayidx = getelementptr inbounds i32, ptr %x, i32 %iv305 %load0 = load i32, ptr %arrayidx, align 4306 %conv0 = zext i32 %load0 to i64307 %rdx.next = add nsw i64 %rdx, %conv0308 %iv.next = add nuw nsw i32 %iv, 1309 %exitcond = icmp eq i32 %iv.next, %n310 br i1 %exitcond, label %exit, label %loop311 312exit:313 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]314 ret i64 %r.0.lcssa315}316 317define i64 @print_mulacc(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {318; CHECK-LABEL: 'print_mulacc'319; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {320; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF321; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF322; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count323; CHECK-NEXT: Live-in ir<%n> = original trip-count324; CHECK-EMPTY:325; CHECK: vector.ph:326; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>327; CHECK-NEXT: Successor(s): vector loop328; CHECK-EMPTY:329; CHECK-NEXT: <x1> vector loop: {330; CHECK-NEXT: vector.body:331; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>332; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>333; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>334; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>335; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]>336; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]>337; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]>338; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]>339; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]>340; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul nsw ir<[[LOAD0]]>, ir<[[LOAD1]]>)341; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>342; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>343; CHECK-NEXT: No successors344; CHECK-NEXT: }345;346entry:347 br label %loop348 349loop:350 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]351 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]352 %arrayidx = getelementptr inbounds i64, ptr %x, i32 %iv353 %load0 = load i64, ptr %arrayidx, align 4354 %arrayidx1 = getelementptr inbounds i64, ptr %y, i32 %iv355 %load1 = load i64, ptr %arrayidx1, align 4356 %mul = mul nsw i64 %load0, %load1357 %rdx.next = add nsw i64 %rdx, %mul358 %iv.next = add nuw nsw i32 %iv, 1359 %exitcond = icmp eq i32 %iv.next, %n360 br i1 %exitcond, label %exit, label %loop361 362exit:363 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]364 ret i64 %r.0.lcssa365}366 367define i64 @print_mulacc_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {368; CHECK-LABEL: 'print_mulacc_extended'369; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {370; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF371; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF372; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count373; CHECK-NEXT: Live-in ir<%n> = original trip-count374; CHECK-EMPTY:375; CHECK: vector.ph:376; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>377; CHECK-NEXT: Successor(s): vector loop378; CHECK-EMPTY:379; CHECK-NEXT: <x1> vector loop: {380; CHECK-NEXT: vector.body:381; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>382; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>383; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>384; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>385; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]>386; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]>387; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]>388; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]>389; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]>390; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.add (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD1]]> sext to i64))391; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>392; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>393; CHECK-NEXT: No successors394; CHECK-NEXT: }395;396entry:397 br label %loop398 399loop:400 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]401 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]402 %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv403 %load0 = load i16, ptr %arrayidx, align 4404 %arrayidx1 = getelementptr inbounds i16, ptr %y, i32 %iv405 %load1 = load i16, ptr %arrayidx1, align 4406 %conv0 = sext i16 %load0 to i32407 %conv1 = sext i16 %load1 to i32408 %mul = mul nsw i32 %conv0, %conv1409 %conv = sext i32 %mul to i64410 %rdx.next = add nsw i64 %rdx, %conv411 %iv.next = add nuw nsw i32 %iv, 1412 %exitcond = icmp eq i32 %iv.next, %n413 br i1 %exitcond, label %exit, label %loop414 415exit:416 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]417 ret i64 %r.0.lcssa418}419 420define i64 @print_extended_sub_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {421; CHECK-LABEL: 'print_extended_sub_reduction'422; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {423; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF424; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF425; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count426; CHECK-NEXT: Live-in ir<%n> = original trip-count427; CHECK-EMPTY:428; CHECK: vector.ph:429; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>430; CHECK-NEXT: Successor(s): vector loop431; CHECK-EMPTY:432; CHECK-NEXT: <x1> vector loop: {433; CHECK-NEXT: vector.body:434; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>435; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>436; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>437; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>438; CHECK-NEXT: vp<[[ADDR:%.+]]> = vector-pointer inbounds ir<%arrayidx>439; CHECK-NEXT: WIDEN ir<[[LOAD:%.+]]> = load vp<[[ADDR]]>440; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.sub (ir<[[LOAD]]> zext to i64)441; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>442; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>443; CHECK-NEXT: No successors444; CHECK-NEXT: }445;446entry:447 br label %loop448 449loop:450 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]451 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]452 %arrayidx = getelementptr inbounds i32, ptr %x, i32 %iv453 %load0 = load i32, ptr %arrayidx, align 4454 %conv0 = zext i32 %load0 to i64455 %rdx.next = sub nsw i64 %rdx, %conv0456 %iv.next = add nuw nsw i32 %iv, 1457 %exitcond = icmp eq i32 %iv.next, %n458 br i1 %exitcond, label %exit, label %loop459 460exit:461 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]462 ret i64 %r.0.lcssa463}464 465define i32 @print_mulacc_sub(ptr %a, ptr %b) {466; CHECK-LABEL: 'print_mulacc_sub'467; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {468; CHECK-NEXT: Live-in vp<%0> = VF469; CHECK-NEXT: Live-in vp<%1> = VF * UF470; CHECK-NEXT: Live-in vp<%2> = vector-trip-count471; CHECK-NEXT: Live-in ir<1024> = original trip-count472; CHECK-EMPTY:473; CHECK-NEXT: ir-bb<entry>:474; CHECK-NEXT: Successor(s): scalar.ph, vector.ph475; CHECK-EMPTY:476; CHECK-NEXT: vector.ph:477; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1>478; CHECK-NEXT: Successor(s): vector loop479; CHECK-EMPTY:480; CHECK-NEXT: <x1> vector loop: {481; CHECK-NEXT: vector.body:482; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next>483; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<%3>, vp<%8>484; CHECK-NEXT: vp<%5> = SCALAR-STEPS vp<%4>, ir<1>, vp<%0>485; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%5>486; CHECK-NEXT: vp<%6> = vector-pointer ir<%gep.a>487; CHECK-NEXT: WIDEN ir<%load.a> = load vp<%6>488; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%5>489; CHECK-NEXT: vp<%7> = vector-pointer ir<%gep.b>490; CHECK-NEXT: WIDEN ir<%load.b> = load vp<%7>491; CHECK-NEXT: EXPRESSION vp<%8> = ir<%accum> + reduce.sub (mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32))492; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%1>493; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%2>494; CHECK-NEXT: No successors495; CHECK-NEXT: }496; CHECK-NEXT: Successor(s): middle.block497; CHECK-EMPTY:498; CHECK-NEXT: middle.block:499; CHECK-NEXT: EMIT vp<%10> = compute-reduction-result ir<%accum>, vp<%8>500; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<%2>501; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>502; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph503; CHECK-EMPTY:504; CHECK-NEXT: ir-bb<exit>:505; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<%10> from middle.block)506; CHECK-NEXT: No successors507; CHECK-EMPTY:508; CHECK-NEXT: scalar.ph:509; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb<entry> ]510; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%10>, middle.block ], [ ir<0>, ir-bb<entry> ]511; CHECK-NEXT: Successor(s): ir-bb<loop>512; CHECK-EMPTY:513; CHECK-NEXT: ir-bb<loop>:514; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)515; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)516; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv517; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1518; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32519; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv520; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1521; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32522; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a523; CHECK-NEXT: IR %add = sub i32 %accum, %mul524; CHECK-NEXT: IR %iv.next = add i64 %iv, 1525; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024526; CHECK-NEXT: No successors527; CHECK-NEXT: }528; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {529; CHECK-NEXT: Live-in ir<1024> = vector-trip-count530; CHECK-NEXT: Live-in ir<1024> = original trip-count531; CHECK-EMPTY:532; CHECK-NEXT: ir-bb<entry>:533; CHECK-NEXT: Successor(s): vector.ph534; CHECK-EMPTY:535; CHECK-NEXT: vector.ph:536; CHECK-NEXT: Successor(s): vector.body537; CHECK-EMPTY:538; CHECK-NEXT: vector.body:539; CHECK-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ]540; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi ir<0>, ir<%add>541; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%index>542; CHECK-NEXT: WIDEN ir<%load.a> = load ir<%gep.a>543; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%index>544; CHECK-NEXT: WIDEN ir<%load.b> = load ir<%gep.b>545; CHECK-NEXT: WIDEN-CAST ir<%ext.b> = zext ir<%load.b> to i32546; CHECK-NEXT: WIDEN-CAST ir<%ext.a> = zext ir<%load.a> to i32547; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%ext.b>, ir<%ext.a>548; CHECK-NEXT: REDUCE ir<%add> = ir<%accum> + reduce.sub (ir<%mul>)549; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<4>550; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, ir<1024>551; CHECK-NEXT: Successor(s): middle.block, vector.body552; CHECK-EMPTY:553; CHECK-NEXT: middle.block:554; CHECK-NEXT: EMIT vp<[[RED_RESULT:%.+]]> = compute-reduction-result ir<%accum>, ir<%add>555; CHECK-NEXT: Successor(s): ir-bb<exit>556; CHECK-EMPTY:557; CHECK-NEXT: ir-bb<exit>:558; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[RED_RESULT]]> from middle.block)559; CHECK-NEXT: No successors560; CHECK-NEXT: }561entry:562 br label %loop563 564loop:565 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]566 %accum = phi i32 [ 0, %entry ], [ %add, %loop ]567 %gep.a = getelementptr i8, ptr %a, i64 %iv568 %load.a = load i8, ptr %gep.a, align 1569 %ext.a = zext i8 %load.a to i32570 %gep.b = getelementptr i8, ptr %b, i64 %iv571 %load.b = load i8, ptr %gep.b, align 1572 %ext.b = zext i8 %load.b to i32573 %mul = mul i32 %ext.b, %ext.a574 %add = sub i32 %accum, %mul575 %iv.next = add i64 %iv, 1576 %exitcond.not = icmp eq i64 %iv.next, 1024577 br i1 %exitcond.not, label %exit, label %loop578 579exit:580 ret i32 %add581}582 583define i32 @print_mulacc_negated(ptr %a, ptr %b) {584; CHECK-LABEL: 'print_mulacc_negated'585; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {586; CHECK-NEXT: Live-in vp<%0> = VF587; CHECK-NEXT: Live-in vp<%1> = VF * UF588; CHECK-NEXT: Live-in vp<%2> = vector-trip-count589; CHECK-NEXT: Live-in ir<1024> = original trip-count590; CHECK-EMPTY:591; CHECK-NEXT: ir-bb<entry>:592; CHECK-NEXT: Successor(s): scalar.ph, vector.ph593; CHECK-EMPTY:594; CHECK-NEXT: vector.ph:595; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1>596; CHECK-NEXT: Successor(s): vector loop597; CHECK-EMPTY:598; CHECK-NEXT: <x1> vector loop: {599; CHECK-NEXT: vector.body:600; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next>601; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<%3>, vp<%8>602; CHECK-NEXT: vp<%5> = SCALAR-STEPS vp<%4>, ir<1>, vp<%0>603; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%5>604; CHECK-NEXT: vp<%6> = vector-pointer ir<%gep.a>605; CHECK-NEXT: WIDEN ir<%load.a> = load vp<%6>606; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%5>607; CHECK-NEXT: vp<%7> = vector-pointer ir<%gep.b>608; CHECK-NEXT: WIDEN ir<%load.b> = load vp<%7>609; CHECK-NEXT: EXPRESSION vp<%8> = ir<%accum> + reduce.add (sub (0, mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32)))610; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%1>611; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%2>612; CHECK-NEXT: No successors613; CHECK-NEXT: }614; CHECK-NEXT: Successor(s): middle.block615; CHECK-EMPTY:616; CHECK-NEXT: middle.block:617; CHECK-NEXT: EMIT vp<%10> = compute-reduction-result ir<%accum>, vp<%8>618; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<%2>619; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>620; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph621; CHECK-EMPTY:622; CHECK-NEXT: ir-bb<exit>:623; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<%10> from middle.block)624; CHECK-NEXT: No successors625; CHECK-EMPTY:626; CHECK-NEXT: scalar.ph:627; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb<entry> ]628; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%10>, middle.block ], [ ir<0>, ir-bb<entry> ]629; CHECK-NEXT: Successor(s): ir-bb<loop>630; CHECK-EMPTY:631; CHECK-NEXT: ir-bb<loop>:632; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)633; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)634; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv635; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1636; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32637; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv638; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1639; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32640; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a641; CHECK-NEXT: IR %sub = sub i32 0, %mul642; CHECK-NEXT: IR %add = add i32 %accum, %sub643; CHECK-NEXT: IR %iv.next = add i64 %iv, 1644; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024645; CHECK-NEXT: No successors646; CHECK-NEXT: }647; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {648; CHECK-NEXT: Live-in ir<1024> = vector-trip-count649; CHECK-NEXT: Live-in ir<1024> = original trip-count650; CHECK-EMPTY:651; CHECK-NEXT: ir-bb<entry>:652; CHECK-NEXT: Successor(s): vector.ph653; CHECK-EMPTY:654; CHECK-NEXT: vector.ph:655; CHECK-NEXT: Successor(s): vector.body656; CHECK-EMPTY:657; CHECK-NEXT: vector.body:658; CHECK-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ]659; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi ir<0>, ir<%add>660; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%index>661; CHECK-NEXT: WIDEN ir<%load.a> = load ir<%gep.a>662; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%index>663; CHECK-NEXT: WIDEN ir<%load.b> = load ir<%gep.b>664; CHECK-NEXT: WIDEN-CAST ir<%ext.b> = zext ir<%load.b> to i32665; CHECK-NEXT: WIDEN-CAST ir<%ext.a> = zext ir<%load.a> to i32666; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%ext.b>, ir<%ext.a>667; CHECK-NEXT: WIDEN ir<%sub> = sub ir<0>, ir<%mul>668; CHECK-NEXT: REDUCE ir<%add> = ir<%accum> + reduce.add (ir<%sub>)669; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<4>670; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, ir<1024>671; CHECK-NEXT: Successor(s): middle.block, vector.body672; CHECK-EMPTY:673; CHECK-NEXT: middle.block:674; CHECK-NEXT: EMIT vp<[[RED_RESULT:%.+]]> = compute-reduction-result ir<%accum>, ir<%add>675; CHECK-NEXT: Successor(s): ir-bb<exit>676; CHECK-EMPTY:677; CHECK-NEXT: ir-bb<exit>:678; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[RED_RESULT]]> from middle.block)679; CHECK-NEXT: No successors680; CHECK-NEXT: }681entry:682 br label %loop683 684loop:685 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]686 %accum = phi i32 [ 0, %entry ], [ %add, %loop ]687 %gep.a = getelementptr i8, ptr %a, i64 %iv688 %load.a = load i8, ptr %gep.a, align 1689 %ext.a = zext i8 %load.a to i32690 %gep.b = getelementptr i8, ptr %b, i64 %iv691 %load.b = load i8, ptr %gep.b, align 1692 %ext.b = zext i8 %load.b to i32693 %mul = mul i32 %ext.b, %ext.a694 %sub = sub i32 0, %mul695 %add = add i32 %accum, %sub696 %iv.next = add i64 %iv, 1697 %exitcond.not = icmp eq i64 %iv.next, 1024698 br i1 %exitcond.not, label %exit, label %loop699 700exit:701 ret i32 %add702}703 704define i64 @print_mulacc_sub_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {705; CHECK-LABEL: 'print_mulacc_sub_extended'706; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {707; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF708; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF709; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count710; CHECK-NEXT: Live-in ir<%n> = original trip-count711; CHECK-EMPTY:712; CHECK: vector.ph:713; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>714; CHECK-NEXT: Successor(s): vector loop715; CHECK-EMPTY:716; CHECK-NEXT: <x1> vector loop: {717; CHECK-NEXT: vector.body:718; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>719; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>720; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>721; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>722; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]>723; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]>724; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]>725; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]>726; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]>727; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.sub (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD1]]> sext to i64))728; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>729; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>730; CHECK-NEXT: No successors731; CHECK-NEXT: }732;733entry:734 br label %loop735 736loop:737 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]738 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]739 %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv740 %load0 = load i16, ptr %arrayidx, align 4741 %arrayidx1 = getelementptr inbounds i16, ptr %y, i32 %iv742 %load1 = load i16, ptr %arrayidx1, align 4743 %conv0 = sext i16 %load0 to i32744 %conv1 = sext i16 %load1 to i32745 %mul = mul nsw i32 %conv0, %conv1746 %conv = sext i32 %mul to i64747 %rdx.next = sub nsw i64 %rdx, %conv748 %iv.next = add nuw nsw i32 %iv, 1749 %exitcond = icmp eq i32 %iv.next, %n750 br i1 %exitcond, label %exit, label %loop751 752exit:753 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]754 ret i64 %r.0.lcssa755}756 757define i64 @print_mulacc_duplicate_extends(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {758; CHECK-LABEL: 'print_mulacc_duplicate_extends'759; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {760; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF761; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF762; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count763; CHECK-NEXT: Live-in ir<%n> = original trip-count764; CHECK-EMPTY:765; CHECK: vector.ph:766; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>767; CHECK-NEXT: Successor(s): vector loop768; CHECK-EMPTY:769; CHECK-NEXT: <x1> vector loop: {770; CHECK-NEXT: vector.body:771; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>772; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>773; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>774; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>775; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]>776; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]>777; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.sub (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD0]]> sext to i64))778; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]>779; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>780; CHECK-NEXT: No successors781; CHECK-NEXT: }782;783entry:784 br label %loop785 786loop:787 %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]788 %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ]789 %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv790 %load0 = load i16, ptr %arrayidx, align 4791 %conv0 = sext i16 %load0 to i32792 %mul = mul nsw i32 %conv0, %conv0793 %conv = sext i32 %mul to i64794 %rdx.next = sub nsw i64 %rdx, %conv795 %iv.next = add nuw nsw i32 %iv, 1796 %exitcond = icmp eq i32 %iv.next, %n797 br i1 %exitcond, label %exit, label %loop798 799exit:800 %r.0.lcssa = phi i64 [ %rdx.next, %loop ]801 ret i64 %r.0.lcssa802}803 804define i32 @print_mulacc_extended_const(ptr %start, ptr %end) {805; CHECK-LABEL: 'print_mulacc_extended_const'806; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {807; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF808; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF809; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count810; CHECK-NEXT: vp<%3> = original trip-count811; CHECK-EMPTY:812; CHECK-NEXT: ir-bb<entry>:813; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))814; CHECK-NEXT: Successor(s): scalar.ph, vector.ph815; CHECK-EMPTY:816; CHECK-NEXT: vector.ph:817; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1>818; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>819; CHECK-NEXT: Successor(s): vector loop820; CHECK-EMPTY:821; CHECK-NEXT: <x1> vector loop: {822; CHECK-NEXT: vector.body:823; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>824; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>825; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>826; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]>827; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep>828; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]>829; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul (ir<%l> zext to i32), (ir<63> zext to i32))830; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>831; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>832; CHECK-NEXT: No successors833; CHECK-NEXT: }834; CHECK-NEXT: Successor(s): middle.block835; CHECK-EMPTY:836; CHECK-NEXT: middle.block:837; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result ir<[[RDX]]>, vp<[[RDX_NEXT]]>838; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]>839; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>840entry:841 br label %loop842 843loop:844 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]845 %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]846 %l = load i8, ptr %ptr.iv, align 1847 %l.ext = zext i8 %l to i32848 %mul = mul i32 %l.ext, 63849 %red.next = add i32 %red, %mul850 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1851 %ec = icmp eq ptr %ptr.iv, %end852 br i1 %ec, label %exit, label %loop853 854exit:855 ret i32 %red.next856}857 858define i32 @print_mulacc_extended_const_lhs(ptr %start, ptr %end) {859; CHECK-LABEL: 'print_mulacc_extended_const_lhs'860; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {861; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF862; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF863; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count864; CHECK-NEXT: vp<%3> = original trip-count865; CHECK-EMPTY:866; CHECK-NEXT: ir-bb<entry>:867; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))868; CHECK-NEXT: Successor(s): scalar.ph, vector.ph869; CHECK-EMPTY:870; CHECK-NEXT: vector.ph:871; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1>872; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>873; CHECK-NEXT: Successor(s): vector loop874; CHECK-EMPTY:875; CHECK-NEXT: <x1> vector loop: {876; CHECK-NEXT: vector.body:877; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>878; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>879; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>880; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]>881; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep>882; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]>883; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = zext ir<%l> to i32884; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul ir<63>, ir<%l.ext>)885; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>886; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>887; CHECK-NEXT: No successors888; CHECK-NEXT: }889; CHECK-NEXT: Successor(s): middle.block890; CHECK-EMPTY:891; CHECK-NEXT: middle.block:892; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result ir<[[RDX]]>, vp<[[RDX_NEXT]]>893; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]>894; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>895entry:896 br label %loop897 898loop:899 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]900 %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]901 %l = load i8, ptr %ptr.iv, align 1902 %l.ext = zext i8 %l to i32903 %mul = mul i32 63, %l.ext904 %red.next = add i32 %red, %mul905 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1906 %ec = icmp eq ptr %ptr.iv, %end907 br i1 %ec, label %exit, label %loop908 909exit:910 ret i32 %red.next911}912 913; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 128914define i32 @print_mulacc_not_extended_const(ptr %start, ptr %end) {915; CHECK-LABEL: 'print_mulacc_not_extended_const'916; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {917; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF918; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF919; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count920; CHECK-NEXT: vp<%3> = original trip-count921; CHECK-EMPTY:922; CHECK-NEXT: ir-bb<entry>:923; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))924; CHECK-NEXT: Successor(s): scalar.ph, vector.ph925; CHECK-EMPTY:926; CHECK-NEXT: vector.ph:927; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1>928; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>929; CHECK-NEXT: Successor(s): vector loop930; CHECK-EMPTY:931; CHECK-NEXT: <x1> vector loop: {932; CHECK-NEXT: vector.body:933; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>934; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>935; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>936; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]>937; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep>938; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]>939; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i32940; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul ir<%l.ext>, ir<128>)941; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>942; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>943; CHECK-NEXT: No successors944; CHECK-NEXT: }945; CHECK-NEXT: Successor(s): middle.block946; CHECK-EMPTY:947; CHECK-NEXT: middle.block:948; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result ir<[[RDX:%.+]]>, vp<[[RDX_NEXT]]>949; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]>950; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>951entry:952 br label %loop953 954loop:955 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]956 %red = phi i32 [ 0, %entry ], [ %red.next, %loop ]957 %l = load i8, ptr %ptr.iv, align 1958 %l.ext = sext i8 %l to i32959 %mul = mul i32 %l.ext, 128960 %red.next = add i32 %red, %mul961 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1962 %ec = icmp eq ptr %ptr.iv, %end963 br i1 %ec, label %exit, label %loop964 965exit:966 %red.next.lcssa = phi i32 [ %red.next, %loop ]967 ret i32 %red.next.lcssa968}969 970define i64 @print_ext_mulacc_extended_const(ptr %start, ptr %end) {971; CHECK-LABEL: 'print_ext_mulacc_extended_const'972; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {973; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF974; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF975; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count976; CHECK-NEXT: vp<%3> = original trip-count977; CHECK-EMPTY:978; CHECK-NEXT: ir-bb<entry>:979; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))980; CHECK-NEXT: Successor(s): scalar.ph, vector.ph981; CHECK-EMPTY:982; CHECK-NEXT: vector.ph:983; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1>984; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>985; CHECK-NEXT: Successor(s): vector loop986; CHECK-EMPTY:987; CHECK-NEXT: <x1> vector loop: {988; CHECK-NEXT: vector.body:989; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>990; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>991; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>992; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]>993; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep>994; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]>995; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul (ir<%l> zext to i64), (ir<63> zext to i64))996; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>997; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>998; CHECK-NEXT: No successors999; CHECK-NEXT: }1000; CHECK-NEXT: Successor(s): middle.block1001; CHECK-EMPTY:1002; CHECK-NEXT: middle.block:1003; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result ir<[[RDX]]>, vp<[[RDX_NEXT]]>1004; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]>1005; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>1006entry:1007 br label %loop1008 1009loop:1010 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]1011 %red = phi i64 [ 0, %entry ], [ %red.next, %loop ]1012 %l = load i8, ptr %ptr.iv, align 11013 %l.ext = zext i8 %l to i321014 %mul = mul i32 %l.ext, 631015 %mul.ext = zext i32 %mul to i641016 %red.next = add i64 %red, %mul.ext1017 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 11018 %ec = icmp eq ptr %ptr.iv, %end1019 br i1 %ec, label %exit, label %loop1020 1021exit:1022 ret i64 %red.next1023}1024 1025; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 1281026define i64 @print_ext_mulacc_not_extended_const(ptr %start, ptr %end) {1027; CHECK-LABEL: 'print_ext_mulacc_not_extended_const'1028; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {1029; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF1030; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF1031; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count1032; CHECK-NEXT: vp<%3> = original trip-count1033; CHECK-EMPTY:1034; CHECK-NEXT: ir-bb<entry>:1035; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))1036; CHECK-NEXT: Successor(s): scalar.ph, vector.ph1037; CHECK-EMPTY:1038; CHECK-NEXT: vector.ph:1039; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1>1040; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>1041; CHECK-NEXT: Successor(s): vector loop1042; CHECK-EMPTY:1043; CHECK-NEXT: <x1> vector loop: {1044; CHECK-NEXT: vector.body:1045; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]>1046; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]>1047; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>1048; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]>1049; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep>1050; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]>1051; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i321052; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%l.ext>, ir<128>1053; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (ir<%mul> sext to i64)1054; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>1055; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>1056; CHECK-NEXT: No successors1057; CHECK-NEXT: }1058; CHECK-NEXT: Successor(s): middle.block1059; CHECK-EMPTY:1060; CHECK-NEXT: middle.block:1061; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result ir<[[RDX]]>, vp<[[RDX_NEXT]]>1062; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]>1063; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>1064entry:1065 br label %loop1066 1067loop:1068 %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ]1069 %red = phi i64 [ 0, %entry ], [ %red.next, %loop ]1070 %l = load i8, ptr %ptr.iv, align 11071 %l.ext = sext i8 %l to i321072 %mul = mul i32 %l.ext, 1281073 %mul.ext = sext i32 %mul to i641074 %red.next = add i64 %red, %mul.ext1075 %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 11076 %ec = icmp eq ptr %ptr.iv, %end1077 br i1 %ec, label %exit, label %loop1078 1079exit:1080 %red.next.lcssa = phi i64 [ %red.next, %loop ]1081 ret i64 %red.next.lcssa1082}1083 1084; This reduce.add(ext(mul(ext(A), ext(B)))) can't be turned into an1085; ExtMulAccReduction VPExpressionRecipe since the mul has two users.1086; It can however be turned into an ExtendedReduction since that one doesn't1087; modify the mul's operands.1088define i64 @print_ext_mul_two_uses(i64 %n, ptr %a, i16 %b, i32 %c) {1089; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {1090; CHECK-NEXT: Live-in vp<%0> = VF * UF1091; CHECK-NEXT: Live-in vp<%1> = vector-trip-count1092; CHECK-NEXT: vp<%2> = original trip-count1093; CHECK-EMPTY:1094; CHECK-NEXT: ir-bb<entry>:1095; CHECK-NEXT: EMIT vp<%2> = EXPAND SCEV (1 + %n)1096; CHECK-NEXT: Successor(s): scalar.ph, vector.ph1097; CHECK-EMPTY:1098; CHECK-NEXT: vector.ph:1099; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1>1100; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext ir<%b> to i321101; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%conv>, ir<%conv>1102; CHECK-NEXT: Successor(s): vector loop1103; CHECK-EMPTY:1104; CHECK-NEXT: <x1> vector loop: {1105; CHECK-NEXT: vector.body:1106; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next>1107; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%res2> = phi vp<%3>, vp<%5>1108; CHECK-NEXT: CLONE ir<%load> = load ir<%a>1109; CHECK-NEXT: WIDEN-CAST ir<%load.ext> = sext ir<%load> to i321110; CHECK-NEXT: WIDEN-CAST ir<%load.ext.ext> = sext ir<%load.ext> to i641111; CHECK-NEXT: EXPRESSION vp<%5> = ir<%res2> + reduce.add (ir<%mul> zext to i64)1112; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%0>1113; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%1>1114; CHECK-NEXT: No successors1115; CHECK-NEXT: }1116; CHECK-NEXT: Successor(s): middle.block1117; CHECK-EMPTY:1118; CHECK-NEXT: middle.block:1119; CHECK-NEXT: EMIT vp<%7> = compute-reduction-result ir<%res2>, vp<%5>1120; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-element ir<%load.ext.ext>1121; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%2>, vp<%1>1122; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>1123; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph1124; CHECK-EMPTY:1125; CHECK-NEXT: ir-bb<exit>:1126; CHECK-NEXT: IR %add.lcssa = phi i64 [ %add, %loop ] (extra operand: vp<%7> from middle.block)1127; CHECK-NEXT: No successors1128; CHECK-EMPTY:1129; CHECK-NEXT: scalar.ph:1130; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%1>, middle.block ], [ ir<0>, ir-bb<entry> ]1131; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<0>, ir-bb<entry> ]1132; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%7>, middle.block ], [ ir<0>, ir-bb<entry> ]1133; CHECK-NEXT: Successor(s): ir-bb<loop>1134; CHECK-EMPTY:1135; CHECK-NEXT: ir-bb<loop>:1136; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)1137; CHECK-NEXT: IR %res1 = phi i64 [ 0, %entry ], [ %load.ext.ext, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph)1138; CHECK-NEXT: IR %res2 = phi i64 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)1139; CHECK-NEXT: IR %load = load i16, ptr %a, align 21140; CHECK-NEXT: IR %iv.next = add i64 %iv, 11141; CHECK-NEXT: IR %conv = sext i16 %b to i321142; CHECK-NEXT: IR %mul = mul i32 %conv, %conv1143; CHECK-NEXT: IR %mul.ext = zext i32 %mul to i641144; CHECK-NEXT: IR %add = add i64 %res2, %mul.ext1145; CHECK-NEXT: IR %second_use = or i32 %mul, %c1146; CHECK-NEXT: IR %load.ext = sext i16 %load to i321147; CHECK-NEXT: IR %load.ext.ext = sext i32 %load.ext to i641148; CHECK-NEXT: IR %exitcond740.not = icmp eq i64 %iv, %n1149; CHECK-NEXT: No successors1150; CHECK-NEXT: }1151entry:1152 br label %loop1153 1154loop:1155 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]1156 %res1 = phi i64 [ 0, %entry ], [ %load.ext.ext, %loop ]1157 %res2 = phi i64 [ 0, %entry ], [ %add, %loop ]1158 %load = load i16, ptr %a, align 21159 %iv.next = add i64 %iv, 11160 %conv = sext i16 %b to i321161 %mul = mul i32 %conv, %conv1162 %mul.ext = zext i32 %mul to i641163 %add = add i64 %res2, %mul.ext1164 %second_use = or i32 %mul, %c ; this value is otherwise unused, but that's sufficient for the test1165 %load.ext = sext i16 %load to i321166 %load.ext.ext = sext i32 %load.ext to i641167 %exitcond740.not = icmp eq i64 %iv, %n1168 br i1 %exitcond740.not, label %exit, label %loop1169 1170exit:1171 ret i64 %add1172}1173