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1; REQUIRES: asserts2 3; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -debug -disable-output %s 2>&1 | FileCheck %s4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"6 7; Make sure recipes with side-effects are not sunk.8define void @sink_with_sideeffects(i1 %c, ptr %ptr) {9; CHECK-LABEL: sink_with_sideeffects10; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {11; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF12; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF13; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count14; CHECK-NEXT: ir<1024> = original trip-count15; CHECK-EMPTY:16; CHECK-NEXT: ir-bb<entry>:17; CHECK-NEXT: Successor(s): scalar.ph, vector.ph18; CHECK-EMPTY:19; CHECK-NEXT: vector.ph:20; CHECK-NEXT: vp<[[END:%.+]]> = DERIVED-IV ir<1024> + vp<[[VEC_TC]]> * ir<-1>21; CHECK-NEXT: Successor(s): vector loop22; CHECK-EMPTY:23; CHECK-NEXT: <x1> vector loop: {24; CHECK-NEXT: vector.body:25; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION26; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>27; CHECK-NEXT: CLONE ir<%tmp2> = getelementptr ir<%ptr>, vp<[[STEPS]]>28; CHECK-NEXT: CLONE ir<%tmp3> = load ir<%tmp2>29; CHECK-NEXT: CLONE store ir<0>, ir<%tmp2>30; CHECK-NEXT: Successor(s): pred.store31 32; CHECK: <xVFxUF> pred.store: {33; CHECK-NEXT: pred.store.entry:34; CHECK-NEXT: BRANCH-ON-MASK ir<%c>35; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue36 37; CHECK: pred.store.if:38; CHECK-NEXT: CLONE store ir<%tmp3>, ir<%tmp2>39; CHECK-NEXT: Successor(s): pred.store.continue40 41; CHECK: pred.store.continue:42; CHECK-NEXT: No successors43; CHECK-NEXT: }44 45; CHECK: if.then.0:46; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>47; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>48; CHECK-NEXT: No successors49; CHECK-NEXT: }50; CHECK-NEXT: Successor(s): middle.block51; CHECK-EMPTY:52; CHECK-NEXT: middle.block:53; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1024>, vp<[[VEC_TC]]>54; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>55; CHECK-NEXT: Successor(s): ir-bb<for.end>, scalar.ph56; CHECK-EMPTY:57; CHECK-NEXT: ir-bb<for.end>:58; CHECK-NEXT: No successors59; CHECK-EMPTY:60; CHECK-NEXT: scalar.ph:61; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME1:%.+]]> = phi [ vp<[[VEC_TC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]62; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME2:%.+]]>.1 = phi [ vp<[[END]]>, middle.block ], [ ir<1024>, ir-bb<entry> ]63; CHECK-NEXT: Successor(s): ir-bb<for.body>64; CHECK-EMPTY:65; CHECK-NEXT: ir-bb<for.body>:66; CHECK-NEXT: IR %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ] (extra operand: vp<[[RESUME1]]> from scalar.ph)67; CHECK-NEXT: IR %tmp1 = phi i64 [ %tmp7, %for.inc ], [ 1024, %entry ] (extra operand: vp<[[RESUME2]]>.1 from scalar.ph)68; CHECK: IR %tmp5 = trunc i32 %tmp4 to i869; CHECK-NEXT: No successors70; CHECK-NEXT: }71;72entry:73 br label %for.body74 75for.body:76 %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ]77 %tmp1 = phi i64 [ %tmp7, %for.inc ], [ 1024, %entry ]78 %tmp2 = getelementptr i8, ptr %ptr, i64 %tmp079 %tmp3 = load i8, ptr %tmp2, align 180 store i8 0, ptr %tmp281 %tmp4 = zext i8 %tmp3 to i3282 %tmp5 = trunc i32 %tmp4 to i883 br i1 %c, label %if.then, label %for.inc84 85if.then:86 store i8 %tmp5, ptr %tmp2, align 187 br label %for.inc88 89for.inc:90 %tmp6 = add nuw nsw i64 %tmp0, 191 %tmp7 = add i64 %tmp1, -192 %tmp8 = icmp eq i64 %tmp7, 093 br i1 %tmp8, label %for.end, label %for.body94 95for.end:96 ret void97}98