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1; RUN: opt < %s -passes=loop-vectorize -enable-vplan-native-path -vplan-build-stress-test -debug-only=vplan -disable-output 2>&1 | FileCheck %s2; REQUIRES: asserts3 4; Verify that the stress testing flag for the VPlan H-CFG builder works as5; expected with and without enabling the VPlan H-CFG Verifier.6 7; CHECK: VPlan 'Plain CFG8 9target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"10 11define void @foo(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) {12entry:13 %cmp32 = icmp sgt i32 %N, 014 br i1 %cmp32, label %outer.ph, label %for.end1515 16outer.ph:17 %cmp230 = icmp sgt i32 %M, 018 %0 = sext i32 %M to i6419 %wide.trip.count = zext i32 %M to i6420 %wide.trip.count38 = zext i32 %N to i6421 br label %outer.body22 23outer.body:24 %indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ]25 br i1 %cmp230, label %inner.ph, label %outer.inc26 27inner.ph:28 %1 = mul nsw i64 %indvars.iv35, %029 br label %inner.body30 31inner.body:32 %indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ]33 %2 = add nsw i64 %indvars.iv, %134 %arrayidx = getelementptr inbounds i32, ptr %b, i64 %235 %3 = load i32, ptr %arrayidx, align 436 %arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %237 store i32 %3, ptr %arrayidx12, align 438 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 139 %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count40 br i1 %exitcond, label %outer.inc, label %inner.body41 42outer.inc:43 %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 144 %exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count3845 br i1 %exitcond39, label %for.end15, label %outer.body46 47for.end15:48 ret void49}50