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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes="default<O3>" -S %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"5target triple = "aarch64"6 7%struct.cmplx_int16_t = type { i16, i16 }8%struct.compressed_data_8bit = type { i8, [24 x i8] }9 10define dso_local noundef i32 @_Z33block_scaling_decompr_8bitjPK27compressed_data_8bitP20cmplx_int16_tPKS2_(i32 noundef %n_prb, ptr noundef %src, ptr noundef %dst, ptr noundef %scale) #0 {11; CHECK-LABEL: define dso_local noundef i32 @_Z33block_scaling_decompr_8bitjPK27compressed_data_8bitP20cmplx_int16_tPKS2_(12; CHECK-SAME: i32 noundef [[N_PRB:%.*]], ptr noundef readonly captures(none) [[SRC:%.*]], ptr noundef writeonly captures(none) [[DST:%.*]], ptr noundef readonly captures(address_is_null) [[SCALE:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: [[ENTRY:.*:]]14; CHECK-NEXT: [[CMP47_NOT:%.*]] = icmp eq i32 [[N_PRB]], 015; CHECK-NEXT: br i1 [[CMP47_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY_LR_PH:.*]]16; CHECK: [[FOR_BODY_LR_PH]]:17; CHECK-NEXT: [[CMP31_NOT:%.*]] = icmp eq ptr [[SCALE]], null18; CHECK-NEXT: [[WIDE_TRIP_COUNT58:%.*]] = zext i32 [[N_PRB]] to i6419; CHECK-NEXT: br i1 [[CMP31_NOT]], label %[[FOR_BODY_US:.*]], label %[[FOR_BODY:.*]]20; CHECK: [[FOR_BODY_US]]:21; CHECK-NEXT: [[INDVARS_IV55:%.*]] = phi i64 [ [[INDVARS_IV_NEXT56:%.*]], %[[FOR_BODY_US]] ], [ 0, %[[FOR_BODY_LR_PH]] ]22; CHECK-NEXT: [[DST_ADDR_052_US:%.*]] = phi ptr [ [[DST_ADDR_1_US:%.*]], %[[FOR_BODY_US]] ], [ [[DST]], %[[FOR_BODY_LR_PH]] ]23; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds nuw [[STRUCT_COMPRESSED_DATA_8BIT:%.*]], ptr [[SRC]], i64 [[INDVARS_IV55]]24; CHECK-NEXT: [[MANTISSA_US:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX_US]], i64 125; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[MANTISSA_US]], align 126; CHECK-NEXT: [[VMOVL_I59_US:%.*]] = sext <8 x i8> [[TMP0]] to <8 x i16>27; CHECK-NEXT: [[ARRAYIDX7_US:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX_US]], i64 928; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[ARRAYIDX7_US]], align 129; CHECK-NEXT: [[VMOVL_I56_US:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>30; CHECK-NEXT: [[ARRAYIDX15_US:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX_US]], i64 1731; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[ARRAYIDX15_US]], align 132; CHECK-NEXT: [[VMOVL_I_US:%.*]] = sext <8 x i8> [[TMP2]] to <8 x i16>33; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX_US]], align 134; CHECK-NEXT: [[CONV_US:%.*]] = sext i8 [[TMP3]] to i1635; CHECK-NEXT: [[MUL_US:%.*]] = shl nsw i16 [[CONV_US]], 136; CHECK-NEXT: [[VECINIT_I79_US:%.*]] = insertelement <8 x i16> poison, i16 [[MUL_US]], i64 037; CHECK-NEXT: [[VECINIT7_I86_US:%.*]] = shufflevector <8 x i16> [[VECINIT_I79_US]], <8 x i16> poison, <8 x i32> zeroinitializer38; CHECK-NEXT: [[MUL_I87_US:%.*]] = mul <8 x i16> [[VECINIT7_I86_US]], [[VMOVL_I59_US]]39; CHECK-NEXT: [[MUL_I74_US:%.*]] = mul <8 x i16> [[VECINIT7_I86_US]], [[VMOVL_I56_US]]40; CHECK-NEXT: [[MUL_I_US:%.*]] = mul <8 x i16> [[VECINIT7_I86_US]], [[VMOVL_I_US]]41; CHECK-NEXT: store <8 x i16> [[MUL_I87_US]], ptr [[DST_ADDR_052_US]], align 242; CHECK-NEXT: [[ADD_PTR47_US:%.*]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052_US]], i64 1643; CHECK-NEXT: store <8 x i16> [[MUL_I74_US]], ptr [[ADD_PTR47_US]], align 244; CHECK-NEXT: [[ADD_PTR50_US:%.*]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052_US]], i64 3245; CHECK-NEXT: store <8 x i16> [[MUL_I_US]], ptr [[ADD_PTR50_US]], align 246; CHECK-NEXT: [[DST_ADDR_1_US]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052_US]], i64 4847; CHECK-NEXT: [[INDVARS_IV_NEXT56]] = add nuw nsw i64 [[INDVARS_IV55]], 148; CHECK-NEXT: [[EXITCOND59_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT56]], [[WIDE_TRIP_COUNT58]]49; CHECK-NEXT: br i1 [[EXITCOND59_NOT]], label %[[FOR_END]], label %[[FOR_BODY_US]], !llvm.loop [[LOOP4:![0-9]+]]50; CHECK: [[FOR_BODY]]:51; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_LR_PH]] ]52; CHECK-NEXT: [[DST_ADDR_052:%.*]] = phi ptr [ [[DST_ADDR_1:%.*]], %[[FOR_BODY]] ], [ [[DST]], %[[FOR_BODY_LR_PH]] ]53; CHECK-NEXT: [[AGG_TMP_COERCE_050:%.*]] = phi i64 [ [[AGG_TMP_COERCE_0_INSERT_INSERT:%.*]], %[[FOR_BODY]] ], [ undef, %[[FOR_BODY_LR_PH]] ]54; CHECK-NEXT: [[AGG_TMP42_COERCE_049:%.*]] = phi i64 [ [[AGG_TMP42_COERCE_0_INSERT_INSERT:%.*]], %[[FOR_BODY]] ], [ undef, %[[FOR_BODY_LR_PH]] ]55; CHECK-NEXT: [[AGG_TMP37_COERCE_048:%.*]] = phi i64 [ [[AGG_TMP37_COERCE_0_INSERT_INSERT:%.*]], %[[FOR_BODY]] ], [ undef, %[[FOR_BODY_LR_PH]] ]56; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [[STRUCT_COMPRESSED_DATA_8BIT]], ptr [[SRC]], i64 [[INDVARS_IV]]57; CHECK-NEXT: [[MANTISSA:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 158; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[MANTISSA]], align 159; CHECK-NEXT: [[VMOVL_I59:%.*]] = sext <8 x i8> [[TMP4]] to <8 x i16>60; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 961; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i8>, ptr [[ARRAYIDX7]], align 162; CHECK-NEXT: [[VMOVL_I56:%.*]] = sext <8 x i8> [[TMP5]] to <8 x i16>63; CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 1764; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i8>, ptr [[ARRAYIDX15]], align 165; CHECK-NEXT: [[VMOVL_I:%.*]] = sext <8 x i8> [[TMP6]] to <8 x i16>66; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[ARRAYIDX]], align 167; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i1668; CHECK-NEXT: [[MUL:%.*]] = shl nsw i16 [[CONV]], 169; CHECK-NEXT: [[VECINIT_I79:%.*]] = insertelement <8 x i16> poison, i16 [[MUL]], i64 070; CHECK-NEXT: [[VECINIT7_I86:%.*]] = shufflevector <8 x i16> [[VECINIT_I79]], <8 x i16> poison, <8 x i32> zeroinitializer71; CHECK-NEXT: [[MUL_I87:%.*]] = mul <8 x i16> [[VECINIT7_I86]], [[VMOVL_I59]]72; CHECK-NEXT: [[MUL_I74:%.*]] = mul <8 x i16> [[VECINIT7_I86]], [[VMOVL_I56]]73; CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[VECINIT7_I86]], [[VMOVL_I]]74; CHECK-NEXT: [[AGG_TMP_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr [[SCALE]], align 275; CHECK-NEXT: [[AGG_TMP_COERCE_0_INSERT_EXT:%.*]] = zext i32 [[AGG_TMP_SROA_0_0_COPYLOAD]] to i6476; CHECK-NEXT: [[AGG_TMP_COERCE_0_INSERT_MASK:%.*]] = and i64 [[AGG_TMP_COERCE_050]], -429496729677; CHECK-NEXT: [[AGG_TMP_COERCE_0_INSERT_INSERT]] = or disjoint i64 [[AGG_TMP_COERCE_0_INSERT_MASK]], [[AGG_TMP_COERCE_0_INSERT_EXT]]78; CHECK-NEXT: [[CALL33:%.*]] = tail call fastcc noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef [[MUL_I87]], i64 [[AGG_TMP_COERCE_0_INSERT_INSERT]])79; CHECK-NEXT: store <8 x i16> [[CALL33]], ptr [[DST_ADDR_052]], align 280; CHECK-NEXT: [[AGG_TMP37_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr [[SCALE]], align 281; CHECK-NEXT: [[AGG_TMP37_COERCE_0_INSERT_EXT:%.*]] = zext i32 [[AGG_TMP37_SROA_0_0_COPYLOAD]] to i6482; CHECK-NEXT: [[AGG_TMP37_COERCE_0_INSERT_MASK:%.*]] = and i64 [[AGG_TMP37_COERCE_048]], -429496729683; CHECK-NEXT: [[AGG_TMP37_COERCE_0_INSERT_INSERT]] = or disjoint i64 [[AGG_TMP37_COERCE_0_INSERT_MASK]], [[AGG_TMP37_COERCE_0_INSERT_EXT]]84; CHECK-NEXT: [[CALL38:%.*]] = tail call fastcc noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef [[MUL_I74]], i64 [[AGG_TMP37_COERCE_0_INSERT_INSERT]])85; CHECK-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052]], i64 1686; CHECK-NEXT: store <8 x i16> [[CALL38]], ptr [[ARRAYIDX39]], align 287; CHECK-NEXT: [[AGG_TMP42_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr [[SCALE]], align 288; CHECK-NEXT: [[AGG_TMP42_COERCE_0_INSERT_EXT:%.*]] = zext i32 [[AGG_TMP42_SROA_0_0_COPYLOAD]] to i6489; CHECK-NEXT: [[AGG_TMP42_COERCE_0_INSERT_MASK:%.*]] = and i64 [[AGG_TMP42_COERCE_049]], -429496729690; CHECK-NEXT: [[AGG_TMP42_COERCE_0_INSERT_INSERT]] = or disjoint i64 [[AGG_TMP42_COERCE_0_INSERT_MASK]], [[AGG_TMP42_COERCE_0_INSERT_EXT]]91; CHECK-NEXT: [[CALL43:%.*]] = tail call fastcc noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef [[MUL_I]], i64 [[AGG_TMP42_COERCE_0_INSERT_INSERT]])92; CHECK-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052]], i64 3293; CHECK-NEXT: store <8 x i16> [[CALL43]], ptr [[ARRAYIDX44]], align 294; CHECK-NEXT: [[DST_ADDR_1]] = getelementptr inbounds nuw i8, ptr [[DST_ADDR_052]], i64 4895; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 196; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT58]]97; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_END]], label %[[FOR_BODY]], !llvm.loop [[LOOP4]]98; CHECK: [[FOR_END]]:99; CHECK-NEXT: ret i32 0100;101entry:102 %__p0.addr.i75 = alloca <8 x i16>, align 16103 %__p1.addr.i76 = alloca i16, align 2104 %__ret.i77 = alloca <8 x i16>, align 16105 %.compoundliteral.i78 = alloca <8 x i16>, align 16106 %__p0.addr.i62 = alloca <8 x i16>, align 16107 %__p1.addr.i63 = alloca i16, align 2108 %__ret.i64 = alloca <8 x i16>, align 16109 %.compoundliteral.i65 = alloca <8 x i16>, align 16110 %__p0.addr.i60 = alloca <8 x i16>, align 16111 %__p1.addr.i = alloca i16, align 2112 %__ret.i61 = alloca <8 x i16>, align 16113 %.compoundliteral.i = alloca <8 x i16>, align 16114 %__p0.addr.i57 = alloca <8 x i8>, align 8115 %__ret.i58 = alloca <8 x i16>, align 16116 %__p0.addr.i54 = alloca <8 x i8>, align 8117 %__ret.i55 = alloca <8 x i16>, align 16118 %__p0.addr.i = alloca <8 x i8>, align 8119 %__ret.i = alloca <8 x i16>, align 16120 %n_prb.addr = alloca i32, align 4121 %src.addr = alloca ptr, align 8122 %dst.addr = alloca ptr, align 8123 %scale.addr = alloca ptr, align 8124 %i = alloca i32, align 4125 %prb_comp_in = alloca [3 x <8 x i16>], align 16126 %__ret = alloca <8 x i8>, align 8127 %tmp = alloca <8 x i8>, align 8128 %__ret3 = alloca <8 x i8>, align 8129 %tmp8 = alloca <8 x i8>, align 8130 %__ret11 = alloca <8 x i8>, align 8131 %tmp16 = alloca <8 x i8>, align 8132 %prb_decomp = alloca [3 x <8 x i16>], align 16133 %scaling_factor = alloca i16, align 2134 %__s1 = alloca <8 x i16>, align 16135 %agg.tmp = alloca %struct.cmplx_int16_t, align 2136 %agg.tmp.coerce = alloca i64, align 8137 %__s135 = alloca <8 x i16>, align 16138 %agg.tmp37 = alloca %struct.cmplx_int16_t, align 2139 %agg.tmp37.coerce = alloca i64, align 8140 %__s140 = alloca <8 x i16>, align 16141 %agg.tmp42 = alloca %struct.cmplx_int16_t, align 2142 %agg.tmp42.coerce = alloca i64, align 8143 %__s145 = alloca <8 x i16>, align 16144 %__s148 = alloca <8 x i16>, align 16145 %__s151 = alloca <8 x i16>, align 16146 store i32 %n_prb, ptr %n_prb.addr, align 4147 store ptr %src, ptr %src.addr, align 8148 store ptr %dst, ptr %dst.addr, align 8149 store ptr %scale, ptr %scale.addr, align 8150 store i32 0, ptr %i, align 4151 br label %for.cond152 153for.cond: ; preds = %for.inc, %entry154 %0 = load i32, ptr %i, align 4155 %1 = load i32, ptr %n_prb.addr, align 4156 %cmp = icmp ult i32 %0, %1157 br i1 %cmp, label %for.body, label %for.end158 159for.body: ; preds = %for.cond160 %2 = load ptr, ptr %src.addr, align 8161 %3 = load i32, ptr %i, align 4162 %idxprom = zext i32 %3 to i64163 %arrayidx = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %2, i64 %idxprom164 %mantissa = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %arrayidx, i32 0, i32 1165 %arrayidx1 = getelementptr inbounds [24 x i8], ptr %mantissa, i64 0, i64 0166 %4 = load <8 x i8>, ptr %arrayidx1, align 1167 store <8 x i8> %4, ptr %__ret, align 8168 %5 = load <8 x i8>, ptr %__ret, align 8169 store <8 x i8> %5, ptr %tmp, align 8170 %6 = load <8 x i8>, ptr %tmp, align 8171 store <8 x i8> %6, ptr %__p0.addr.i57, align 8172 %7 = load <8 x i8>, ptr %__p0.addr.i57, align 8173 %vmovl.i59 = sext <8 x i8> %7 to <8 x i16>174 store <8 x i16> %vmovl.i59, ptr %__ret.i58, align 16175 %8 = load <8 x i16>, ptr %__ret.i58, align 16176 %arrayidx2 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 0177 store <8 x i16> %8, ptr %arrayidx2, align 16178 %9 = load ptr, ptr %src.addr, align 8179 %10 = load i32, ptr %i, align 4180 %idxprom4 = zext i32 %10 to i64181 %arrayidx5 = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %9, i64 %idxprom4182 %mantissa6 = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %arrayidx5, i32 0, i32 1183 %arrayidx7 = getelementptr inbounds [24 x i8], ptr %mantissa6, i64 0, i64 8184 %11 = load <8 x i8>, ptr %arrayidx7, align 1185 store <8 x i8> %11, ptr %__ret3, align 8186 %12 = load <8 x i8>, ptr %__ret3, align 8187 store <8 x i8> %12, ptr %tmp8, align 8188 %13 = load <8 x i8>, ptr %tmp8, align 8189 store <8 x i8> %13, ptr %__p0.addr.i54, align 8190 %14 = load <8 x i8>, ptr %__p0.addr.i54, align 8191 %vmovl.i56 = sext <8 x i8> %14 to <8 x i16>192 store <8 x i16> %vmovl.i56, ptr %__ret.i55, align 16193 %15 = load <8 x i16>, ptr %__ret.i55, align 16194 %arrayidx10 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 1195 store <8 x i16> %15, ptr %arrayidx10, align 16196 %16 = load ptr, ptr %src.addr, align 8197 %17 = load i32, ptr %i, align 4198 %idxprom12 = zext i32 %17 to i64199 %arrayidx13 = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %16, i64 %idxprom12200 %mantissa14 = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %arrayidx13, i32 0, i32 1201 %arrayidx15 = getelementptr inbounds [24 x i8], ptr %mantissa14, i64 0, i64 16202 %18 = load <8 x i8>, ptr %arrayidx15, align 1203 store <8 x i8> %18, ptr %__ret11, align 8204 %19 = load <8 x i8>, ptr %__ret11, align 8205 store <8 x i8> %19, ptr %tmp16, align 8206 %20 = load <8 x i8>, ptr %tmp16, align 8207 store <8 x i8> %20, ptr %__p0.addr.i, align 8208 %21 = load <8 x i8>, ptr %__p0.addr.i, align 8209 %vmovl.i = sext <8 x i8> %21 to <8 x i16>210 store <8 x i16> %vmovl.i, ptr %__ret.i, align 16211 %22 = load <8 x i16>, ptr %__ret.i, align 16212 %arrayidx18 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 2213 store <8 x i16> %22, ptr %arrayidx18, align 16214 %23 = load ptr, ptr %src.addr, align 8215 %24 = load i32, ptr %i, align 4216 %idxprom19 = zext i32 %24 to i64217 %arrayidx20 = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %23, i64 %idxprom19218 %exp = getelementptr inbounds nuw %struct.compressed_data_8bit, ptr %arrayidx20, i32 0, i32 0219 %25 = load i8, ptr %exp, align 1220 %conv = sext i8 %25 to i32221 %mul = mul nsw i32 %conv, 2222 %conv21 = trunc i32 %mul to i16223 store i16 %conv21, ptr %scaling_factor, align 2224 %arrayidx22 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 0225 %26 = load <8 x i16>, ptr %arrayidx22, align 16226 %27 = load i16, ptr %scaling_factor, align 2227 store <8 x i16> %26, ptr %__p0.addr.i75, align 16228 store i16 %27, ptr %__p1.addr.i76, align 2229 %28 = load <8 x i16>, ptr %__p0.addr.i75, align 16230 %29 = load i16, ptr %__p1.addr.i76, align 2231 %vecinit.i79 = insertelement <8 x i16> poison, i16 %29, i32 0232 %30 = load i16, ptr %__p1.addr.i76, align 2233 %vecinit1.i80 = insertelement <8 x i16> %vecinit.i79, i16 %30, i32 1234 %31 = load i16, ptr %__p1.addr.i76, align 2235 %vecinit2.i81 = insertelement <8 x i16> %vecinit1.i80, i16 %31, i32 2236 %32 = load i16, ptr %__p1.addr.i76, align 2237 %vecinit3.i82 = insertelement <8 x i16> %vecinit2.i81, i16 %32, i32 3238 %33 = load i16, ptr %__p1.addr.i76, align 2239 %vecinit4.i83 = insertelement <8 x i16> %vecinit3.i82, i16 %33, i32 4240 %34 = load i16, ptr %__p1.addr.i76, align 2241 %vecinit5.i84 = insertelement <8 x i16> %vecinit4.i83, i16 %34, i32 5242 %35 = load i16, ptr %__p1.addr.i76, align 2243 %vecinit6.i85 = insertelement <8 x i16> %vecinit5.i84, i16 %35, i32 6244 %36 = load i16, ptr %__p1.addr.i76, align 2245 %vecinit7.i86 = insertelement <8 x i16> %vecinit6.i85, i16 %36, i32 7246 store <8 x i16> %vecinit7.i86, ptr %.compoundliteral.i78, align 16247 %37 = load <8 x i16>, ptr %.compoundliteral.i78, align 16248 %mul.i87 = mul <8 x i16> %28, %37249 store <8 x i16> %mul.i87, ptr %__ret.i77, align 16250 %38 = load <8 x i16>, ptr %__ret.i77, align 16251 %arrayidx24 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 0252 store <8 x i16> %38, ptr %arrayidx24, align 16253 %arrayidx25 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 1254 %39 = load <8 x i16>, ptr %arrayidx25, align 16255 %40 = load i16, ptr %scaling_factor, align 2256 store <8 x i16> %39, ptr %__p0.addr.i62, align 16257 store i16 %40, ptr %__p1.addr.i63, align 2258 %41 = load <8 x i16>, ptr %__p0.addr.i62, align 16259 %42 = load i16, ptr %__p1.addr.i63, align 2260 %vecinit.i66 = insertelement <8 x i16> poison, i16 %42, i32 0261 %43 = load i16, ptr %__p1.addr.i63, align 2262 %vecinit1.i67 = insertelement <8 x i16> %vecinit.i66, i16 %43, i32 1263 %44 = load i16, ptr %__p1.addr.i63, align 2264 %vecinit2.i68 = insertelement <8 x i16> %vecinit1.i67, i16 %44, i32 2265 %45 = load i16, ptr %__p1.addr.i63, align 2266 %vecinit3.i69 = insertelement <8 x i16> %vecinit2.i68, i16 %45, i32 3267 %46 = load i16, ptr %__p1.addr.i63, align 2268 %vecinit4.i70 = insertelement <8 x i16> %vecinit3.i69, i16 %46, i32 4269 %47 = load i16, ptr %__p1.addr.i63, align 2270 %vecinit5.i71 = insertelement <8 x i16> %vecinit4.i70, i16 %47, i32 5271 %48 = load i16, ptr %__p1.addr.i63, align 2272 %vecinit6.i72 = insertelement <8 x i16> %vecinit5.i71, i16 %48, i32 6273 %49 = load i16, ptr %__p1.addr.i63, align 2274 %vecinit7.i73 = insertelement <8 x i16> %vecinit6.i72, i16 %49, i32 7275 store <8 x i16> %vecinit7.i73, ptr %.compoundliteral.i65, align 16276 %50 = load <8 x i16>, ptr %.compoundliteral.i65, align 16277 %mul.i74 = mul <8 x i16> %41, %50278 store <8 x i16> %mul.i74, ptr %__ret.i64, align 16279 %51 = load <8 x i16>, ptr %__ret.i64, align 16280 %arrayidx27 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 1281 store <8 x i16> %51, ptr %arrayidx27, align 16282 %arrayidx28 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_comp_in, i64 0, i64 2283 %52 = load <8 x i16>, ptr %arrayidx28, align 16284 %53 = load i16, ptr %scaling_factor, align 2285 store <8 x i16> %52, ptr %__p0.addr.i60, align 16286 store i16 %53, ptr %__p1.addr.i, align 2287 %54 = load <8 x i16>, ptr %__p0.addr.i60, align 16288 %55 = load i16, ptr %__p1.addr.i, align 2289 %vecinit.i = insertelement <8 x i16> poison, i16 %55, i32 0290 %56 = load i16, ptr %__p1.addr.i, align 2291 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %56, i32 1292 %57 = load i16, ptr %__p1.addr.i, align 2293 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %57, i32 2294 %58 = load i16, ptr %__p1.addr.i, align 2295 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %58, i32 3296 %59 = load i16, ptr %__p1.addr.i, align 2297 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %59, i32 4298 %60 = load i16, ptr %__p1.addr.i, align 2299 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %60, i32 5300 %61 = load i16, ptr %__p1.addr.i, align 2301 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %61, i32 6302 %62 = load i16, ptr %__p1.addr.i, align 2303 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %62, i32 7304 store <8 x i16> %vecinit7.i, ptr %.compoundliteral.i, align 16305 %63 = load <8 x i16>, ptr %.compoundliteral.i, align 16306 %mul.i = mul <8 x i16> %54, %63307 store <8 x i16> %mul.i, ptr %__ret.i61, align 16308 %64 = load <8 x i16>, ptr %__ret.i61, align 16309 %arrayidx30 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 2310 store <8 x i16> %64, ptr %arrayidx30, align 16311 %65 = load ptr, ptr %scale.addr, align 8312 %cmp31 = icmp ne ptr %65, null313 br i1 %cmp31, label %if.then, label %if.else314 315if.then: ; preds = %for.body316 %arrayidx32 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 0317 %66 = load <8 x i16>, ptr %arrayidx32, align 16318 %67 = load ptr, ptr %scale.addr, align 8319 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %agg.tmp, ptr align 2 %67, i64 4, i1 false)320 call void @llvm.memcpy.p0.p0.i64(ptr align 8 %agg.tmp.coerce, ptr align 2 %agg.tmp, i64 4, i1 false)321 %68 = load i64, ptr %agg.tmp.coerce, align 8322 %call33 = call noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef %66, i64 %68)323 store <8 x i16> %call33, ptr %__s1, align 16324 %69 = load ptr, ptr %dst.addr, align 8325 %arrayidx34 = getelementptr inbounds %struct.cmplx_int16_t, ptr %69, i64 0326 %70 = load <8 x i16>, ptr %__s1, align 16327 %71 = bitcast <8 x i16> %70 to <16 x i8>328 %72 = bitcast <16 x i8> %71 to <8 x i16>329 store <8 x i16> %72, ptr %arrayidx34, align 2330 %arrayidx36 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 1331 %73 = load <8 x i16>, ptr %arrayidx36, align 16332 %74 = load ptr, ptr %scale.addr, align 8333 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %agg.tmp37, ptr align 2 %74, i64 4, i1 false)334 call void @llvm.memcpy.p0.p0.i64(ptr align 8 %agg.tmp37.coerce, ptr align 2 %agg.tmp37, i64 4, i1 false)335 %75 = load i64, ptr %agg.tmp37.coerce, align 8336 %call38 = call noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef %73, i64 %75)337 store <8 x i16> %call38, ptr %__s135, align 16338 %76 = load ptr, ptr %dst.addr, align 8339 %arrayidx39 = getelementptr inbounds %struct.cmplx_int16_t, ptr %76, i64 4340 %77 = load <8 x i16>, ptr %__s135, align 16341 %78 = bitcast <8 x i16> %77 to <16 x i8>342 %79 = bitcast <16 x i8> %78 to <8 x i16>343 store <8 x i16> %79, ptr %arrayidx39, align 2344 %arrayidx41 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 2345 %80 = load <8 x i16>, ptr %arrayidx41, align 16346 %81 = load ptr, ptr %scale.addr, align 8347 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %agg.tmp42, ptr align 2 %81, i64 4, i1 false)348 call void @llvm.memcpy.p0.p0.i64(ptr align 8 %agg.tmp42.coerce, ptr align 2 %agg.tmp42, i64 4, i1 false)349 %82 = load i64, ptr %agg.tmp42.coerce, align 8350 %call43 = call noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef %80, i64 %82)351 store <8 x i16> %call43, ptr %__s140, align 16352 %83 = load ptr, ptr %dst.addr, align 8353 %arrayidx44 = getelementptr inbounds %struct.cmplx_int16_t, ptr %83, i64 8354 %84 = load <8 x i16>, ptr %__s140, align 16355 %85 = bitcast <8 x i16> %84 to <16 x i8>356 %86 = bitcast <16 x i8> %85 to <8 x i16>357 store <8 x i16> %86, ptr %arrayidx44, align 2358 %87 = load ptr, ptr %dst.addr, align 8359 %add.ptr = getelementptr inbounds %struct.cmplx_int16_t, ptr %87, i64 12360 store ptr %add.ptr, ptr %dst.addr, align 8361 br label %if.end362 363if.else: ; preds = %for.body364 %arrayidx46 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 0365 %88 = load <8 x i16>, ptr %arrayidx46, align 16366 store <8 x i16> %88, ptr %__s145, align 16367 %89 = load ptr, ptr %dst.addr, align 8368 %90 = load <8 x i16>, ptr %__s145, align 16369 %91 = bitcast <8 x i16> %90 to <16 x i8>370 %92 = bitcast <16 x i8> %91 to <8 x i16>371 store <8 x i16> %92, ptr %89, align 2372 %93 = load ptr, ptr %dst.addr, align 8373 %add.ptr47 = getelementptr inbounds %struct.cmplx_int16_t, ptr %93, i64 4374 store ptr %add.ptr47, ptr %dst.addr, align 8375 %arrayidx49 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 1376 %94 = load <8 x i16>, ptr %arrayidx49, align 16377 store <8 x i16> %94, ptr %__s148, align 16378 %95 = load ptr, ptr %dst.addr, align 8379 %96 = load <8 x i16>, ptr %__s148, align 16380 %97 = bitcast <8 x i16> %96 to <16 x i8>381 %98 = bitcast <16 x i8> %97 to <8 x i16>382 store <8 x i16> %98, ptr %95, align 2383 %99 = load ptr, ptr %dst.addr, align 8384 %add.ptr50 = getelementptr inbounds %struct.cmplx_int16_t, ptr %99, i64 4385 store ptr %add.ptr50, ptr %dst.addr, align 8386 %arrayidx52 = getelementptr inbounds [3 x <8 x i16>], ptr %prb_decomp, i64 0, i64 2387 %100 = load <8 x i16>, ptr %arrayidx52, align 16388 store <8 x i16> %100, ptr %__s151, align 16389 %101 = load ptr, ptr %dst.addr, align 8390 %102 = load <8 x i16>, ptr %__s151, align 16391 %103 = bitcast <8 x i16> %102 to <16 x i8>392 %104 = bitcast <16 x i8> %103 to <8 x i16>393 store <8 x i16> %104, ptr %101, align 2394 %105 = load ptr, ptr %dst.addr, align 8395 %add.ptr53 = getelementptr inbounds %struct.cmplx_int16_t, ptr %105, i64 4396 store ptr %add.ptr53, ptr %dst.addr, align 8397 br label %if.end398 399if.end: ; preds = %if.else, %if.then400 br label %for.inc401 402for.inc: ; preds = %if.end403 %106 = load i32, ptr %i, align 4404 %inc = add i32 %106, 1405 store i32 %inc, ptr %i, align 4406 br label %for.cond, !llvm.loop !4407 408for.end: ; preds = %for.cond409 ret i32 0410}411 412define internal noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(<8 x i16> noundef %a, i64 %scale.coerce) #0 {413; CHECK-LABEL: define internal fastcc noundef <8 x i16> @_ZL24cmplx_mul_combined_re_im11__Int16x8_t20cmplx_int16_t(414; CHECK-SAME: <8 x i16> noundef [[A:%.*]], i64 [[SCALE_COERCE:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] {415; CHECK-NEXT: [[ENTRY:.*:]]416; CHECK-NEXT: [[SCALE_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[SCALE_COERCE]] to i16417; CHECK-NEXT: [[SCALE_SROA_2_0_EXTRACT_SHIFT36:%.*]] = lshr i64 [[SCALE_COERCE]], 16418; CHECK-NEXT: [[SCALE_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[SCALE_SROA_2_0_EXTRACT_SHIFT36]] to i16419; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>420; CHECK-NEXT: [[VECINIT_I19:%.*]] = insertelement <8 x i16> poison, i16 [[SCALE_SROA_0_0_EXTRACT_TRUNC]], i64 0421; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[SCALE_SROA_2_0_EXTRACT_TRUNC]], i64 0422; CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer423; CHECK-NEXT: [[VQNEGQ_V1_I:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> [[VECINIT7_I]])424; CHECK-NEXT: [[VBSL5_I:%.*]] = shufflevector <8 x i16> [[VQNEGQ_V1_I]], <8 x i16> [[VECINIT_I]], <8 x i32> <i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6, i32 8>425; CHECK-NEXT: [[SHUFFLE_I85:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>426; CHECK-NEXT: [[SHUFFLE_I82:%.*]] = shufflevector <8 x i16> [[VECINIT_I19]], <8 x i16> poison, <4 x i32> zeroinitializer427; CHECK-NEXT: [[VQDMULL_V2_I72:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[SHUFFLE_I85]], <4 x i16> [[SHUFFLE_I82]])428; CHECK-NEXT: [[SHUFFLE_I97:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>429; CHECK-NEXT: [[VQDMULL_V2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[SHUFFLE_I97]], <4 x i16> [[SHUFFLE_I82]])430; CHECK-NEXT: [[SHUFFLE_I79:%.*]] = shufflevector <8 x i16> [[SHUFFLE_I]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>431; CHECK-NEXT: [[SHUFFLE_I76:%.*]] = shufflevector <8 x i16> [[VBSL5_I]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>432; CHECK-NEXT: [[VQDMLAL2_I106:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[SHUFFLE_I79]], <4 x i16> [[SHUFFLE_I76]])433; CHECK-NEXT: [[VQDMLAL_V3_I107:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMULL_V2_I72]], <4 x i32> [[VQDMLAL2_I106]])434; CHECK-NEXT: [[SHUFFLE_I91:%.*]] = shufflevector <8 x i16> [[SHUFFLE_I]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>435; CHECK-NEXT: [[SHUFFLE_I88:%.*]] = shufflevector <8 x i16> [[VBSL5_I]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>436; CHECK-NEXT: [[VQDMLAL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[SHUFFLE_I91]], <4 x i16> [[SHUFFLE_I88]])437; CHECK-NEXT: [[VQDMLAL_V3_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMULL_V2_I]], <4 x i32> [[VQDMLAL2_I]])438; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[VQDMLAL_V3_I107]] to <8 x i16>439; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[VQDMLAL_V3_I]] to <8 x i16>440; CHECK-NEXT: [[SHUFFLE_I61:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>441; CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I61]]442;443entry:444 %__p0.addr.i102 = alloca <4 x i32>, align 16445 %__p1.addr.i103 = alloca <4 x i16>, align 8446 %__p2.addr.i104 = alloca <4 x i16>, align 8447 %__ret.i105 = alloca <4 x i32>, align 16448 %__p0.addr.i98 = alloca <4 x i32>, align 16449 %__p1.addr.i99 = alloca <4 x i16>, align 8450 %__p2.addr.i100 = alloca <4 x i16>, align 8451 %__ret.i101 = alloca <4 x i32>, align 16452 %__p0.addr.i95 = alloca <8 x i16>, align 16453 %__ret.i96 = alloca <4 x i16>, align 8454 %__p0.addr.i92 = alloca <8 x i16>, align 16455 %__ret.i93 = alloca <4 x i16>, align 8456 %__p0.addr.i89 = alloca <8 x i16>, align 16457 %__ret.i90 = alloca <4 x i16>, align 8458 %__p0.addr.i86 = alloca <8 x i16>, align 16459 %__ret.i87 = alloca <4 x i16>, align 8460 %__p0.addr.i83 = alloca <8 x i16>, align 16461 %__ret.i84 = alloca <4 x i16>, align 8462 %__p0.addr.i80 = alloca <8 x i16>, align 16463 %__ret.i81 = alloca <4 x i16>, align 8464 %__p0.addr.i77 = alloca <8 x i16>, align 16465 %__ret.i78 = alloca <4 x i16>, align 8466 %__p0.addr.i74 = alloca <8 x i16>, align 16467 %__ret.i75 = alloca <4 x i16>, align 8468 %__p0.addr.i69 = alloca <4 x i16>, align 8469 %__p1.addr.i70 = alloca <4 x i16>, align 8470 %__ret.i71 = alloca <4 x i32>, align 16471 %__p0.addr.i66 = alloca <4 x i16>, align 8472 %__p1.addr.i67 = alloca <4 x i16>, align 8473 %__ret.i68 = alloca <4 x i32>, align 16474 %__p0.addr.i64 = alloca <4 x i32>, align 16475 %__ret.i65 = alloca <8 x i16>, align 16476 %__p0.addr.i62 = alloca <4 x i32>, align 16477 %__ret.i63 = alloca <8 x i16>, align 16478 %__p0.addr.i58 = alloca <8 x i16>, align 16479 %__p1.addr.i59 = alloca <8 x i16>, align 16480 %__ret.i60 = alloca <8 x i16>, align 16481 %__p0.addr.i51 = alloca <4 x i32>, align 16482 %__p1.addr.i52 = alloca <8 x i16>, align 16483 %__p2.addr.i53 = alloca <8 x i16>, align 16484 %__ret.i54 = alloca <4 x i32>, align 16485 %a.addr.i46 = alloca <4 x i32>, align 16486 %b.addr.i47 = alloca <8 x i16>, align 16487 %c.addr.i = alloca <8 x i16>, align 16488 %__p0.addr.i40 = alloca <8 x i16>, align 16489 %__p1.addr.i41 = alloca <8 x i16>, align 16490 %__ret.i42 = alloca <4 x i32>, align 16491 %a.addr.i = alloca <8 x i16>, align 16492 %b.addr.i = alloca <8 x i16>, align 16493 %__p0.addr.i38 = alloca <8 x i16>, align 16494 %__ret.i39 = alloca <8 x i16>, align 16495 %__p0.addr.i36 = alloca <8 x i16>, align 16496 %__p1.addr.i = alloca <8 x i16>, align 16497 %__p2.addr.i = alloca <8 x i16>, align 16498 %__ret.i37 = alloca <8 x i16>, align 16499 %__p0.addr.i29 = alloca i32, align 4500 %__ret.i30 = alloca <4 x i32>, align 16501 %.compoundliteral.i31 = alloca <4 x i32>, align 16502 %__p0.addr.i27 = alloca <4 x i32>, align 16503 %__ret.i28 = alloca <8 x i16>, align 16504 %__p0.addr.i16 = alloca i16, align 2505 %__ret.i17 = alloca <8 x i16>, align 16506 %.compoundliteral.i18 = alloca <8 x i16>, align 16507 %__p0.addr.i14 = alloca i16, align 2508 %__ret.i15 = alloca <8 x i16>, align 16509 %.compoundliteral.i = alloca <8 x i16>, align 16510 %__p0.addr.i = alloca <8 x i16>, align 16511 %__ret.i = alloca <8 x i16>, align 16512 %scale = alloca %struct.cmplx_int16_t, align 2513 %a.addr = alloca <8 x i16>, align 16514 %a_rev = alloca <8 x i16>, align 16515 %cc = alloca <8 x i16>, align 16516 %dd = alloca <8 x i16>, align 16517 %mult_mask = alloca <8 x i16>, align 16518 %lo32 = alloca <4 x i32>, align 16519 %hi32 = alloca <4 x i32>, align 16520 %coerce.val.ii = trunc i64 %scale.coerce to i32521 store i32 %coerce.val.ii, ptr %scale, align 2522 store <8 x i16> %a, ptr %a.addr, align 16523 %0 = load <8 x i16>, ptr %a.addr, align 16524 store <8 x i16> %0, ptr %__p0.addr.i, align 16525 %1 = load <8 x i16>, ptr %__p0.addr.i, align 16526 %2 = load <8 x i16>, ptr %__p0.addr.i, align 16527 %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>528 store <8 x i16> %shuffle.i, ptr %__ret.i, align 16529 %3 = load <8 x i16>, ptr %__ret.i, align 16530 store <8 x i16> %3, ptr %a_rev, align 16531 %re = getelementptr inbounds nuw %struct.cmplx_int16_t, ptr %scale, i32 0, i32 0532 %4 = load i16, ptr %re, align 2533 store i16 %4, ptr %__p0.addr.i16, align 2534 %5 = load i16, ptr %__p0.addr.i16, align 2535 %vecinit.i19 = insertelement <8 x i16> poison, i16 %5, i32 0536 %6 = load i16, ptr %__p0.addr.i16, align 2537 %vecinit1.i20 = insertelement <8 x i16> %vecinit.i19, i16 %6, i32 1538 %7 = load i16, ptr %__p0.addr.i16, align 2539 %vecinit2.i21 = insertelement <8 x i16> %vecinit1.i20, i16 %7, i32 2540 %8 = load i16, ptr %__p0.addr.i16, align 2541 %vecinit3.i22 = insertelement <8 x i16> %vecinit2.i21, i16 %8, i32 3542 %9 = load i16, ptr %__p0.addr.i16, align 2543 %vecinit4.i23 = insertelement <8 x i16> %vecinit3.i22, i16 %9, i32 4544 %10 = load i16, ptr %__p0.addr.i16, align 2545 %vecinit5.i24 = insertelement <8 x i16> %vecinit4.i23, i16 %10, i32 5546 %11 = load i16, ptr %__p0.addr.i16, align 2547 %vecinit6.i25 = insertelement <8 x i16> %vecinit5.i24, i16 %11, i32 6548 %12 = load i16, ptr %__p0.addr.i16, align 2549 %vecinit7.i26 = insertelement <8 x i16> %vecinit6.i25, i16 %12, i32 7550 store <8 x i16> %vecinit7.i26, ptr %.compoundliteral.i18, align 16551 %13 = load <8 x i16>, ptr %.compoundliteral.i18, align 16552 store <8 x i16> %13, ptr %__ret.i17, align 16553 %14 = load <8 x i16>, ptr %__ret.i17, align 16554 store <8 x i16> %14, ptr %cc, align 16555 %im = getelementptr inbounds nuw %struct.cmplx_int16_t, ptr %scale, i32 0, i32 1556 %15 = load i16, ptr %im, align 2557 store i16 %15, ptr %__p0.addr.i14, align 2558 %16 = load i16, ptr %__p0.addr.i14, align 2559 %vecinit.i = insertelement <8 x i16> poison, i16 %16, i32 0560 %17 = load i16, ptr %__p0.addr.i14, align 2561 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %17, i32 1562 %18 = load i16, ptr %__p0.addr.i14, align 2563 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %18, i32 2564 %19 = load i16, ptr %__p0.addr.i14, align 2565 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %19, i32 3566 %20 = load i16, ptr %__p0.addr.i14, align 2567 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %20, i32 4568 %21 = load i16, ptr %__p0.addr.i14, align 2569 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %21, i32 5570 %22 = load i16, ptr %__p0.addr.i14, align 2571 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %22, i32 6572 %23 = load i16, ptr %__p0.addr.i14, align 2573 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %23, i32 7574 store <8 x i16> %vecinit7.i, ptr %.compoundliteral.i, align 16575 %24 = load <8 x i16>, ptr %.compoundliteral.i, align 16576 store <8 x i16> %24, ptr %__ret.i15, align 16577 %25 = load <8 x i16>, ptr %__ret.i15, align 16578 store <8 x i16> %25, ptr %dd, align 16579 store i32 65535, ptr %__p0.addr.i29, align 4580 %26 = load i32, ptr %__p0.addr.i29, align 4581 %vecinit.i32 = insertelement <4 x i32> poison, i32 %26, i32 0582 %27 = load i32, ptr %__p0.addr.i29, align 4583 %vecinit1.i33 = insertelement <4 x i32> %vecinit.i32, i32 %27, i32 1584 %28 = load i32, ptr %__p0.addr.i29, align 4585 %vecinit2.i34 = insertelement <4 x i32> %vecinit1.i33, i32 %28, i32 2586 %29 = load i32, ptr %__p0.addr.i29, align 4587 %vecinit3.i35 = insertelement <4 x i32> %vecinit2.i34, i32 %29, i32 3588 store <4 x i32> %vecinit3.i35, ptr %.compoundliteral.i31, align 16589 %30 = load <4 x i32>, ptr %.compoundliteral.i31, align 16590 store <4 x i32> %30, ptr %__ret.i30, align 16591 %31 = load <4 x i32>, ptr %__ret.i30, align 16592 store <4 x i32> %31, ptr %__p0.addr.i27, align 16593 %32 = load <4 x i32>, ptr %__p0.addr.i27, align 16594 %33 = bitcast <4 x i32> %32 to <8 x i16>595 store <8 x i16> %33, ptr %__ret.i28, align 16596 %34 = load <8 x i16>, ptr %__ret.i28, align 16597 store <8 x i16> %34, ptr %mult_mask, align 16598 %35 = load <8 x i16>, ptr %mult_mask, align 16599 %36 = load <8 x i16>, ptr %dd, align 16600 store <8 x i16> %36, ptr %__p0.addr.i38, align 16601 %37 = load <8 x i16>, ptr %__p0.addr.i38, align 16602 %38 = bitcast <8 x i16> %37 to <16 x i8>603 %vqnegq_v1.i = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %37)604 %vqnegq_v2.i = bitcast <8 x i16> %vqnegq_v1.i to <16 x i8>605 store <8 x i16> %vqnegq_v1.i, ptr %__ret.i39, align 16606 %39 = load <8 x i16>, ptr %__ret.i39, align 16607 %40 = load <8 x i16>, ptr %dd, align 16608 store <8 x i16> %35, ptr %__p0.addr.i36, align 16609 store <8 x i16> %39, ptr %__p1.addr.i, align 16610 store <8 x i16> %40, ptr %__p2.addr.i, align 16611 %41 = load <8 x i16>, ptr %__p0.addr.i36, align 16612 %42 = bitcast <8 x i16> %41 to <16 x i8>613 %43 = load <8 x i16>, ptr %__p1.addr.i, align 16614 %44 = bitcast <8 x i16> %43 to <16 x i8>615 %45 = load <8 x i16>, ptr %__p2.addr.i, align 16616 %46 = bitcast <8 x i16> %45 to <16 x i8>617 %vbsl3.i = and <8 x i16> %41, %43618 %47 = xor <8 x i16> %41, splat (i16 -1)619 %vbsl4.i = and <8 x i16> %47, %45620 %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i621 store <8 x i16> %vbsl5.i, ptr %__ret.i37, align 16622 %48 = load <8 x i16>, ptr %__ret.i37, align 16623 store <8 x i16> %48, ptr %dd, align 16624 %49 = load <8 x i16>, ptr %a.addr, align 16625 %50 = load <8 x i16>, ptr %cc, align 16626 store <8 x i16> %49, ptr %a.addr.i, align 16627 store <8 x i16> %50, ptr %b.addr.i, align 16628 %51 = load <8 x i16>, ptr %a.addr.i, align 16629 store <8 x i16> %51, ptr %__p0.addr.i83, align 16630 %52 = load <8 x i16>, ptr %__p0.addr.i83, align 16631 %53 = load <8 x i16>, ptr %__p0.addr.i83, align 16632 %shuffle.i85 = shufflevector <8 x i16> %52, <8 x i16> %53, <4 x i32> <i32 0, i32 1, i32 2, i32 3>633 store <4 x i16> %shuffle.i85, ptr %__ret.i84, align 8634 %54 = load <4 x i16>, ptr %__ret.i84, align 8635 %55 = load <8 x i16>, ptr %b.addr.i, align 16636 store <8 x i16> %55, ptr %__p0.addr.i80, align 16637 %56 = load <8 x i16>, ptr %__p0.addr.i80, align 16638 %57 = load <8 x i16>, ptr %__p0.addr.i80, align 16639 %shuffle.i82 = shufflevector <8 x i16> %56, <8 x i16> %57, <4 x i32> <i32 0, i32 1, i32 2, i32 3>640 store <4 x i16> %shuffle.i82, ptr %__ret.i81, align 8641 %58 = load <4 x i16>, ptr %__ret.i81, align 8642 store <4 x i16> %54, ptr %__p0.addr.i69, align 8643 store <4 x i16> %58, ptr %__p1.addr.i70, align 8644 %59 = load <4 x i16>, ptr %__p0.addr.i69, align 8645 %60 = bitcast <4 x i16> %59 to <8 x i8>646 %61 = load <4 x i16>, ptr %__p1.addr.i70, align 8647 %62 = bitcast <4 x i16> %61 to <8 x i8>648 %vqdmull_v2.i72 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %59, <4 x i16> %61)649 %vqdmull_v3.i73 = bitcast <4 x i32> %vqdmull_v2.i72 to <16 x i8>650 store <4 x i32> %vqdmull_v2.i72, ptr %__ret.i71, align 16651 %63 = load <4 x i32>, ptr %__ret.i71, align 16652 store <4 x i32> %63, ptr %lo32, align 16653 %64 = load <8 x i16>, ptr %a.addr, align 16654 %65 = load <8 x i16>, ptr %cc, align 16655 store <8 x i16> %64, ptr %__p0.addr.i40, align 16656 store <8 x i16> %65, ptr %__p1.addr.i41, align 16657 %66 = load <8 x i16>, ptr %__p0.addr.i40, align 16658 store <8 x i16> %66, ptr %__p0.addr.i95, align 16659 %67 = load <8 x i16>, ptr %__p0.addr.i95, align 16660 %68 = load <8 x i16>, ptr %__p0.addr.i95, align 16661 %shuffle.i97 = shufflevector <8 x i16> %67, <8 x i16> %68, <4 x i32> <i32 4, i32 5, i32 6, i32 7>662 store <4 x i16> %shuffle.i97, ptr %__ret.i96, align 8663 %69 = load <4 x i16>, ptr %__ret.i96, align 8664 %70 = load <8 x i16>, ptr %__p1.addr.i41, align 16665 store <8 x i16> %70, ptr %__p0.addr.i92, align 16666 %71 = load <8 x i16>, ptr %__p0.addr.i92, align 16667 %72 = load <8 x i16>, ptr %__p0.addr.i92, align 16668 %shuffle.i94 = shufflevector <8 x i16> %71, <8 x i16> %72, <4 x i32> <i32 4, i32 5, i32 6, i32 7>669 store <4 x i16> %shuffle.i94, ptr %__ret.i93, align 8670 %73 = load <4 x i16>, ptr %__ret.i93, align 8671 store <4 x i16> %69, ptr %__p0.addr.i66, align 8672 store <4 x i16> %73, ptr %__p1.addr.i67, align 8673 %74 = load <4 x i16>, ptr %__p0.addr.i66, align 8674 %75 = bitcast <4 x i16> %74 to <8 x i8>675 %76 = load <4 x i16>, ptr %__p1.addr.i67, align 8676 %77 = bitcast <4 x i16> %76 to <8 x i8>677 %vqdmull_v2.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %74, <4 x i16> %76)678 %vqdmull_v3.i = bitcast <4 x i32> %vqdmull_v2.i to <16 x i8>679 store <4 x i32> %vqdmull_v2.i, ptr %__ret.i68, align 16680 %78 = load <4 x i32>, ptr %__ret.i68, align 16681 store <4 x i32> %78, ptr %__ret.i42, align 16682 %79 = load <4 x i32>, ptr %__ret.i42, align 16683 store <4 x i32> %79, ptr %hi32, align 16684 %80 = load <4 x i32>, ptr %lo32, align 16685 %81 = load <8 x i16>, ptr %a_rev, align 16686 %82 = load <8 x i16>, ptr %dd, align 16687 store <4 x i32> %80, ptr %a.addr.i46, align 16688 store <8 x i16> %81, ptr %b.addr.i47, align 16689 store <8 x i16> %82, ptr %c.addr.i, align 16690 %83 = load <4 x i32>, ptr %a.addr.i46, align 16691 %84 = load <8 x i16>, ptr %b.addr.i47, align 16692 store <8 x i16> %84, ptr %__p0.addr.i77, align 16693 %85 = load <8 x i16>, ptr %__p0.addr.i77, align 16694 %86 = load <8 x i16>, ptr %__p0.addr.i77, align 16695 %shuffle.i79 = shufflevector <8 x i16> %85, <8 x i16> %86, <4 x i32> <i32 0, i32 1, i32 2, i32 3>696 store <4 x i16> %shuffle.i79, ptr %__ret.i78, align 8697 %87 = load <4 x i16>, ptr %__ret.i78, align 8698 %88 = load <8 x i16>, ptr %c.addr.i, align 16699 store <8 x i16> %88, ptr %__p0.addr.i74, align 16700 %89 = load <8 x i16>, ptr %__p0.addr.i74, align 16701 %90 = load <8 x i16>, ptr %__p0.addr.i74, align 16702 %shuffle.i76 = shufflevector <8 x i16> %89, <8 x i16> %90, <4 x i32> <i32 0, i32 1, i32 2, i32 3>703 store <4 x i16> %shuffle.i76, ptr %__ret.i75, align 8704 %91 = load <4 x i16>, ptr %__ret.i75, align 8705 store <4 x i32> %83, ptr %__p0.addr.i102, align 16706 store <4 x i16> %87, ptr %__p1.addr.i103, align 8707 store <4 x i16> %91, ptr %__p2.addr.i104, align 8708 %92 = load <4 x i32>, ptr %__p0.addr.i102, align 16709 %93 = bitcast <4 x i32> %92 to <16 x i8>710 %94 = load <4 x i16>, ptr %__p1.addr.i103, align 8711 %95 = bitcast <4 x i16> %94 to <8 x i8>712 %96 = load <4 x i16>, ptr %__p2.addr.i104, align 8713 %97 = bitcast <4 x i16> %96 to <8 x i8>714 %vqdmlal2.i106 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %94, <4 x i16> %96)715 %vqdmlal_v3.i107 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %92, <4 x i32> %vqdmlal2.i106)716 store <4 x i32> %vqdmlal_v3.i107, ptr %__ret.i105, align 16717 %98 = load <4 x i32>, ptr %__ret.i105, align 16718 store <4 x i32> %98, ptr %lo32, align 16719 %99 = load <4 x i32>, ptr %hi32, align 16720 %100 = load <8 x i16>, ptr %a_rev, align 16721 %101 = load <8 x i16>, ptr %dd, align 16722 store <4 x i32> %99, ptr %__p0.addr.i51, align 16723 store <8 x i16> %100, ptr %__p1.addr.i52, align 16724 store <8 x i16> %101, ptr %__p2.addr.i53, align 16725 %102 = load <4 x i32>, ptr %__p0.addr.i51, align 16726 %103 = load <8 x i16>, ptr %__p1.addr.i52, align 16727 store <8 x i16> %103, ptr %__p0.addr.i89, align 16728 %104 = load <8 x i16>, ptr %__p0.addr.i89, align 16729 %105 = load <8 x i16>, ptr %__p0.addr.i89, align 16730 %shuffle.i91 = shufflevector <8 x i16> %104, <8 x i16> %105, <4 x i32> <i32 4, i32 5, i32 6, i32 7>731 store <4 x i16> %shuffle.i91, ptr %__ret.i90, align 8732 %106 = load <4 x i16>, ptr %__ret.i90, align 8733 %107 = load <8 x i16>, ptr %__p2.addr.i53, align 16734 store <8 x i16> %107, ptr %__p0.addr.i86, align 16735 %108 = load <8 x i16>, ptr %__p0.addr.i86, align 16736 %109 = load <8 x i16>, ptr %__p0.addr.i86, align 16737 %shuffle.i88 = shufflevector <8 x i16> %108, <8 x i16> %109, <4 x i32> <i32 4, i32 5, i32 6, i32 7>738 store <4 x i16> %shuffle.i88, ptr %__ret.i87, align 8739 %110 = load <4 x i16>, ptr %__ret.i87, align 8740 store <4 x i32> %102, ptr %__p0.addr.i98, align 16741 store <4 x i16> %106, ptr %__p1.addr.i99, align 8742 store <4 x i16> %110, ptr %__p2.addr.i100, align 8743 %111 = load <4 x i32>, ptr %__p0.addr.i98, align 16744 %112 = bitcast <4 x i32> %111 to <16 x i8>745 %113 = load <4 x i16>, ptr %__p1.addr.i99, align 8746 %114 = bitcast <4 x i16> %113 to <8 x i8>747 %115 = load <4 x i16>, ptr %__p2.addr.i100, align 8748 %116 = bitcast <4 x i16> %115 to <8 x i8>749 %vqdmlal2.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %113, <4 x i16> %115)750 %vqdmlal_v3.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %111, <4 x i32> %vqdmlal2.i)751 store <4 x i32> %vqdmlal_v3.i, ptr %__ret.i101, align 16752 %117 = load <4 x i32>, ptr %__ret.i101, align 16753 store <4 x i32> %117, ptr %__ret.i54, align 16754 %118 = load <4 x i32>, ptr %__ret.i54, align 16755 store <4 x i32> %118, ptr %hi32, align 16756 %119 = load <4 x i32>, ptr %lo32, align 16757 store <4 x i32> %119, ptr %__p0.addr.i64, align 16758 %120 = load <4 x i32>, ptr %__p0.addr.i64, align 16759 %121 = bitcast <4 x i32> %120 to <8 x i16>760 store <8 x i16> %121, ptr %__ret.i65, align 16761 %122 = load <8 x i16>, ptr %__ret.i65, align 16762 %123 = load <4 x i32>, ptr %hi32, align 16763 store <4 x i32> %123, ptr %__p0.addr.i62, align 16764 %124 = load <4 x i32>, ptr %__p0.addr.i62, align 16765 %125 = bitcast <4 x i32> %124 to <8 x i16>766 store <8 x i16> %125, ptr %__ret.i63, align 16767 %126 = load <8 x i16>, ptr %__ret.i63, align 16768 store <8 x i16> %122, ptr %__p0.addr.i58, align 16769 store <8 x i16> %126, ptr %__p1.addr.i59, align 16770 %127 = load <8 x i16>, ptr %__p0.addr.i58, align 16771 %128 = load <8 x i16>, ptr %__p1.addr.i59, align 16772 %shuffle.i61 = shufflevector <8 x i16> %127, <8 x i16> %128, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>773 store <8 x i16> %shuffle.i61, ptr %__ret.i60, align 16774 %129 = load <8 x i16>, ptr %__ret.i60, align 16775 ret <8 x i16> %129776}777 778; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)779declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1780 781; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)782declare <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16>) #2783 784; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)785declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) #2786 787; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)788declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) #2789 790attributes #0 = { mustprogress noinline uwtable vscale_range(1,16) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a,-fmv" }791attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }792attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }793 794!llvm.module.flags = !{!0, !1, !2}795!llvm.ident = !{!3}796 797!0 = !{i32 1, !"wchar_size", i32 4}798!1 = !{i32 7, !"uwtable", i32 2}799!2 = !{i32 7, !"frame-pointer", i32 1}800!3 = !{!"clang version 20.0.0git"}801!4 = distinct !{!4, !5}802!5 = !{!"llvm.loop.mustprogress"}803;.804; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}805; CHECK: [[META5]] = !{!"llvm.loop.mustprogress"}806;.807