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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -passes="default<O3>" -S %s | FileCheck %s3 4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"5target triple = "arm64-apple-macosx11.0.0"6 7define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {8; CHECK-LABEL: define void @partial_unroll_forced(9; CHECK-SAME: i32 [[N:%.*]], ptr readonly captures(none) [[SRC:%.*]], ptr noalias writeonly captures(none) [[DST:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: entry:11; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 012; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]13; CHECK: loop.latch.preheader:14; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i6415; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 116; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 117; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP_LATCH_EPIL_PREHEADER:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]]18; CHECK: loop.latch.preheader.new:19; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 214748364620; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]21; CHECK: loop.latch:22; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ]23; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[LOOP_LATCH]] ]24; CHECK-NEXT: [[SRC_IDX:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV]]25; CHECK-NEXT: [[L:%.*]] = load <8 x half>, ptr [[SRC_IDX]], align 1626; CHECK-NEXT: [[DST_IDX:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV]]27; CHECK-NEXT: [[ADD:%.*]] = fadd <8 x half> [[L]], [[L]]28; CHECK-NEXT: store <8 x half> [[ADD]], ptr [[DST_IDX]], align 1629; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 130; CHECK-NEXT: [[SRC_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_NEXT]]31; CHECK-NEXT: [[L_1:%.*]] = load <8 x half>, ptr [[SRC_IDX_1]], align 1632; CHECK-NEXT: [[DST_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_NEXT]]33; CHECK-NEXT: [[ADD_1:%.*]] = fadd <8 x half> [[L_1]], [[L_1]]34; CHECK-NEXT: store <8 x half> [[ADD_1]], ptr [[DST_IDX_1]], align 1635; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 236; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 237; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]38; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]]39; CHECK: exit.loopexit.unr-lcssa:40; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 041; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]]42; CHECK: loop.latch.epil.preheader:43; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ]44; CHECK-NEXT: [[LCMP_MOD4:%.*]] = icmp ne i64 [[XTRAITER]], 045; CHECK-NEXT: tail call void @llvm.assume(i1 [[LCMP_MOD4]])46; CHECK-NEXT: [[SRC_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_UNR]]47; CHECK-NEXT: [[L_EPIL:%.*]] = load <8 x half>, ptr [[SRC_IDX_EPIL]], align 1648; CHECK-NEXT: [[DST_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_UNR]]49; CHECK-NEXT: [[ADD_EPIL:%.*]] = fadd <8 x half> [[L_EPIL]], [[L_EPIL]]50; CHECK-NEXT: store <8 x half> [[ADD_EPIL]], ptr [[DST_IDX_EPIL]], align 1651; CHECK-NEXT: br label [[EXIT]]52; CHECK: exit:53; CHECK-NEXT: ret void54;55entry:56 br label %loop.header57 58loop.header:59 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]60 %cmp14 = icmp slt i32 %iv, %N61 br i1 %cmp14, label %loop.latch, label %exit62 63loop.latch:64 %iv.ext = zext i32 %iv to i6465 %src.idx = getelementptr <8 x half>, ptr %src, i64 %iv.ext66 %l = load <8 x half>, ptr %src.idx, align 1667 %dst.idx = getelementptr <8 x half>, ptr %dst, i64 %iv.ext68 %add = fadd <8 x half> %l, %l69 store <8 x half> %add, ptr %dst.idx, align 1670 %iv.next = add i32 %iv, 171 br label %loop.header, !llvm.loop !072 73exit:74 ret void75}76 77define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src, ptr noalias %dst) {78; CHECK-LABEL: define void @cse_matching_load_from_previous_unrolled_iteration(79; CHECK-SAME: i32 [[N:%.*]], ptr readonly captures(none) [[SRC:%.*]], ptr noalias writeonly captures(none) [[DST:%.*]]) local_unnamed_addr #[[ATTR0]] {80; CHECK-NEXT: entry:81; CHECK-NEXT: [[SRC_4:%.*]] = getelementptr i8, ptr [[SRC]], i64 482; CHECK-NEXT: [[SRC_12:%.*]] = getelementptr i8, ptr [[SRC]], i64 1283; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 084; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]85; CHECK: loop.latch.preheader:86; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i6487; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 188; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 189; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP_LATCH_EPIL_PREHEADER:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]]90; CHECK: loop.latch.preheader.new:91; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 214748364692; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]93; CHECK: loop.latch:94; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ]95; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[LOOP_LATCH]] ]96; CHECK-NEXT: [[GEP_SRC_12:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV]]97; CHECK-NEXT: [[L_12:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12]], align 898; CHECK-NEXT: [[GEP_SRC_4:%.*]] = getelementptr <2 x i32>, ptr [[SRC_4]], i64 [[INDVARS_IV]]99; CHECK-NEXT: [[L_4:%.*]] = load <2 x i32>, ptr [[GEP_SRC_4]], align 8100; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[L_4]], [[L_12]]101; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV]]102; CHECK-NEXT: store <2 x i32> [[MUL]], ptr [[GEP_DST]], align 8103; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1104; CHECK-NEXT: [[GEP_SRC_12_1:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV_NEXT]]105; CHECK-NEXT: [[L_12_1:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12_1]], align 8106; CHECK-NEXT: [[MUL_1:%.*]] = mul <2 x i32> [[L_12]], [[L_12_1]]107; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV_NEXT]]108; CHECK-NEXT: store <2 x i32> [[MUL_1]], ptr [[GEP_DST_1]], align 8109; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2110; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2111; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]112; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]113; CHECK: exit.loopexit.unr-lcssa:114; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0115; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]]116; CHECK: loop.latch.epil.preheader:117; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ]118; CHECK-NEXT: [[LCMP_MOD4:%.*]] = icmp ne i64 [[XTRAITER]], 0119; CHECK-NEXT: tail call void @llvm.assume(i1 [[LCMP_MOD4]])120; CHECK-NEXT: [[GEP_SRC_12_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV_UNR]]121; CHECK-NEXT: [[L_12_EPIL:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12_EPIL]], align 8122; CHECK-NEXT: [[GEP_SRC_4_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[SRC_4]], i64 [[INDVARS_IV_UNR]]123; CHECK-NEXT: [[L_4_EPIL:%.*]] = load <2 x i32>, ptr [[GEP_SRC_4_EPIL]], align 8124; CHECK-NEXT: [[MUL_EPIL:%.*]] = mul <2 x i32> [[L_4_EPIL]], [[L_12_EPIL]]125; CHECK-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV_UNR]]126; CHECK-NEXT: store <2 x i32> [[MUL_EPIL]], ptr [[GEP_DST_EPIL]], align 8127; CHECK-NEXT: br label [[EXIT]]128; CHECK: exit:129; CHECK-NEXT: ret void130;131entry:132 %src.4 = getelementptr i8, ptr %src, i64 4133 %src.12 = getelementptr i8, ptr %src, i64 12134 br label %loop.header135 136loop.header:137 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]138 %cmp14 = icmp slt i32 %iv, %N139 br i1 %cmp14, label %loop.latch, label %exit140 141loop.latch:142 %iv.ext = zext i32 %iv to i64143 %gep.src.12 = getelementptr <2 x i32>, ptr %src.12, i64 %iv.ext144 %l.12 = load <2 x i32>, ptr %gep.src.12, align 8145 %gep.src.4 = getelementptr <2 x i32>, ptr %src.4, i64 %iv.ext146 %l.4 = load <2 x i32>, ptr %gep.src.4, align 8147 %mul = mul <2 x i32> %l.12, %l.4148 %gep.dst = getelementptr <2 x i32>, ptr %dst, i64 %iv.ext149 store <2 x i32> %mul, ptr %gep.dst150 %iv.next = add nuw nsw i32 %iv, 1151 br label %loop.header, !llvm.loop !0152 153exit:154 ret void155}156 157!0 = distinct !{!0, !1, !2}158!1 = !{!"llvm.loop.mustprogress"}159!2 = !{!"llvm.loop.unroll.count", i32 2}160;.161; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}162; CHECK: [[META1]] = !{!"llvm.loop.mustprogress"}163; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}164; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}165;.166