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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -O3 < %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5target triple = "aarch64"6 7; Check that the function gets vectorized.8 9define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) {10; CHECK-LABEL: define range(i32 0, 2) i32 @quant_4x411; CHECK-SAME: (ptr noundef captures(none) [[DCT:%.*]], ptr noundef readonly captures(none) [[MF:%.*]], ptr noundef readonly captures(none) [[BIAS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: entry:13; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DCT]], i64 3214; CHECK-NEXT: [[SCEVGEP23:%.*]] = getelementptr i8, ptr [[BIAS]], i64 3215; CHECK-NEXT: [[SCEVGEP24:%.*]] = getelementptr i8, ptr [[MF]], i64 3216; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP23]]17; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BIAS]], [[SCEVGEP]]18; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]19; CHECK-NEXT: [[BOUND025:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP24]]20; CHECK-NEXT: [[BOUND126:%.*]] = icmp ult ptr [[MF]], [[SCEVGEP]]21; CHECK-NEXT: [[FOUND_CONFLICT27:%.*]] = and i1 [[BOUND025]], [[BOUND126]]22; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT27]]23; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]24; CHECK: vector.body:25; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 1626; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[DCT]], align 2, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]27; CHECK-NEXT: [[WIDE_LOAD29:%.*]] = load <8 x i16>, ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]]28; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32>29; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[WIDE_LOAD29]] to <8 x i32>30; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer31; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD29]], zeroinitializer32; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 1633; CHECK-NEXT: [[WIDE_LOAD30:%.*]] = load <8 x i16>, ptr [[BIAS]], align 2, !alias.scope [[META6:![0-9]+]]34; CHECK-NEXT: [[WIDE_LOAD31:%.*]] = load <8 x i16>, ptr [[TMP5]], align 2, !alias.scope [[META6]]35; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i16> [[WIDE_LOAD30]] to <8 x i32>36; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i16> [[WIDE_LOAD31]] to <8 x i32>37; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 1638; CHECK-NEXT: [[WIDE_LOAD32:%.*]] = load <8 x i16>, ptr [[MF]], align 2, !alias.scope [[META7:![0-9]+]]39; CHECK-NEXT: [[WIDE_LOAD33:%.*]] = load <8 x i16>, ptr [[TMP8]], align 2, !alias.scope [[META7]]40; CHECK-NEXT: [[TMP9:%.*]] = zext <8 x i16> [[WIDE_LOAD32]] to <8 x i32>41; CHECK-NEXT: [[TMP10:%.*]] = zext <8 x i16> [[WIDE_LOAD33]] to <8 x i32>42; CHECK-NEXT: [[TMP11:%.*]] = sub nsw <8 x i32> [[TMP6]], [[TMP1]]43; CHECK-NEXT: [[TMP12:%.*]] = sub nsw <8 x i32> [[TMP7]], [[TMP2]]44; CHECK-NEXT: [[TMP13:%.*]] = mul <8 x i32> [[TMP11]], [[TMP9]]45; CHECK-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP12]], [[TMP10]]46; CHECK-NEXT: [[TMP15:%.*]] = lshr <8 x i32> [[TMP13]], splat (i32 16)47; CHECK-NEXT: [[TMP16:%.*]] = lshr <8 x i32> [[TMP14]], splat (i32 16)48; CHECK-NEXT: [[TMP17:%.*]] = trunc nuw <8 x i32> [[TMP15]] to <8 x i16>49; CHECK-NEXT: [[TMP18:%.*]] = trunc nuw <8 x i32> [[TMP16]] to <8 x i16>50; CHECK-NEXT: [[TMP19:%.*]] = sub <8 x i16> zeroinitializer, [[TMP17]]51; CHECK-NEXT: [[TMP20:%.*]] = sub <8 x i16> zeroinitializer, [[TMP18]]52; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw <8 x i32> [[TMP6]], [[TMP1]]53; CHECK-NEXT: [[TMP22:%.*]] = add nuw nsw <8 x i32> [[TMP7]], [[TMP2]]54; CHECK-NEXT: [[TMP23:%.*]] = mul <8 x i32> [[TMP21]], [[TMP9]]55; CHECK-NEXT: [[TMP24:%.*]] = mul <8 x i32> [[TMP22]], [[TMP10]]56; CHECK-NEXT: [[TMP25:%.*]] = lshr <8 x i32> [[TMP23]], splat (i32 16)57; CHECK-NEXT: [[TMP26:%.*]] = lshr <8 x i32> [[TMP24]], splat (i32 16)58; CHECK-NEXT: [[TMP27:%.*]] = trunc nuw <8 x i32> [[TMP25]] to <8 x i16>59; CHECK-NEXT: [[TMP28:%.*]] = trunc nuw <8 x i32> [[TMP26]] to <8 x i16>60; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP27]], <8 x i16> [[TMP19]]61; CHECK-NEXT: [[PREDPHI34:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP28]], <8 x i16> [[TMP20]]62; CHECK-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope [[META0]], !noalias [[META3]]63; CHECK-NEXT: store <8 x i16> [[PREDPHI34]], ptr [[TMP0]], align 2, !alias.scope [[META0]], !noalias [[META3]]64; CHECK-NEXT: [[BIN_RDX35:%.*]] = or <8 x i16> [[PREDPHI34]], [[PREDPHI]]65; CHECK-NEXT: [[TMP29:%.*]] = tail call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[BIN_RDX35]])66; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]]67; CHECK: for.cond.cleanup:68; CHECK-NEXT: [[OR_LCSSA_IN:%.*]] = phi i16 [ [[TMP29]], [[VECTOR_BODY]] ], [ [[OR_1551:%.*]], [[IF_END_15:%.*]] ]69; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i16 [[OR_LCSSA_IN]], 070; CHECK-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL]] to i3271; CHECK-NEXT: ret i32 [[LNOT_EXT]]72; CHECK: for.body:73; CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[DCT]], align 274; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP30]] to i3275; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP30]], 076; CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[BIAS]], align 277; CHECK-NEXT: [[CONV5:%.*]] = zext i16 [[TMP31]] to i3278; CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[MF]], align 279; CHECK-NEXT: [[CONV11:%.*]] = zext i16 [[TMP32]] to i3280; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]81; CHECK: if.then:82; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV5]], [[CONV]]83; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ADD]], [[CONV11]]84; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 1685; CHECK-NEXT: [[CONV12:%.*]] = trunc nuw i32 [[SHR]] to i1686; CHECK-NEXT: br label [[IF_END:%.*]]87; CHECK: if.else:88; CHECK-NEXT: [[ADD21:%.*]] = sub nsw i32 [[CONV5]], [[CONV]]89; CHECK-NEXT: [[MUL25:%.*]] = mul i32 [[ADD21]], [[CONV11]]90; CHECK-NEXT: [[SHR26:%.*]] = lshr i32 [[MUL25]], 1691; CHECK-NEXT: [[TMP33:%.*]] = trunc nuw i32 [[SHR26]] to i1692; CHECK-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP33]]93; CHECK-NEXT: br label [[IF_END]]94; CHECK: if.end:95; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i16 [ [[CONV28]], [[IF_ELSE]] ], [ [[CONV12]], [[IF_THEN]] ]96; CHECK-NEXT: store i16 [[STOREMERGE]], ptr [[DCT]], align 297; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 298; CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 299; CHECK-NEXT: [[CONV_1:%.*]] = sext i16 [[TMP34]] to i32100; CHECK-NEXT: [[CMP1_1:%.*]] = icmp sgt i16 [[TMP34]], 0101; CHECK-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 2102; CHECK-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX4_1]], align 2103; CHECK-NEXT: [[CONV5_1:%.*]] = zext i16 [[TMP35]] to i32104; CHECK-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 2105; CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[ARRAYIDX10_1]], align 2106; CHECK-NEXT: [[CONV11_1:%.*]] = zext i16 [[TMP36]] to i32107; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]]108; CHECK: if.else.1:109; CHECK-NEXT: [[ADD21_1:%.*]] = sub nsw i32 [[CONV5_1]], [[CONV_1]]110; CHECK-NEXT: [[MUL25_1:%.*]] = mul i32 [[ADD21_1]], [[CONV11_1]]111; CHECK-NEXT: [[SHR26_1:%.*]] = lshr i32 [[MUL25_1]], 16112; CHECK-NEXT: [[TMP37:%.*]] = trunc nuw i32 [[SHR26_1]] to i16113; CHECK-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP37]]114; CHECK-NEXT: br label [[IF_END_1:%.*]]115; CHECK: if.then.1:116; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[CONV5_1]], [[CONV_1]]117; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[ADD_1]], [[CONV11_1]]118; CHECK-NEXT: [[SHR_1:%.*]] = lshr i32 [[MUL_1]], 16119; CHECK-NEXT: [[CONV12_1:%.*]] = trunc nuw i32 [[SHR_1]] to i16120; CHECK-NEXT: br label [[IF_END_1]]121; CHECK: if.end.1:122; CHECK-NEXT: [[STOREMERGE_1:%.*]] = phi i16 [ [[CONV28_1]], [[IF_ELSE_1]] ], [ [[CONV12_1]], [[IF_THEN_1]] ]123; CHECK-NEXT: store i16 [[STOREMERGE_1]], ptr [[ARRAYIDX_1]], align 2124; CHECK-NEXT: [[OR_137:%.*]] = or i16 [[STOREMERGE]], [[STOREMERGE_1]]125; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 4126; CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 2127; CHECK-NEXT: [[CONV_2:%.*]] = sext i16 [[TMP38]] to i32128; CHECK-NEXT: [[CMP1_2:%.*]] = icmp sgt i16 [[TMP38]], 0129; CHECK-NEXT: [[ARRAYIDX4_2:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 4130; CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[ARRAYIDX4_2]], align 2131; CHECK-NEXT: [[CONV5_2:%.*]] = zext i16 [[TMP39]] to i32132; CHECK-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 4133; CHECK-NEXT: [[TMP40:%.*]] = load i16, ptr [[ARRAYIDX10_2]], align 2134; CHECK-NEXT: [[CONV11_2:%.*]] = zext i16 [[TMP40]] to i32135; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]]136; CHECK: if.else.2:137; CHECK-NEXT: [[ADD21_2:%.*]] = sub nsw i32 [[CONV5_2]], [[CONV_2]]138; CHECK-NEXT: [[MUL25_2:%.*]] = mul i32 [[ADD21_2]], [[CONV11_2]]139; CHECK-NEXT: [[SHR26_2:%.*]] = lshr i32 [[MUL25_2]], 16140; CHECK-NEXT: [[TMP41:%.*]] = trunc nuw i32 [[SHR26_2]] to i16141; CHECK-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP41]]142; CHECK-NEXT: br label [[IF_END_2:%.*]]143; CHECK: if.then.2:144; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[CONV5_2]], [[CONV_2]]145; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[ADD_2]], [[CONV11_2]]146; CHECK-NEXT: [[SHR_2:%.*]] = lshr i32 [[MUL_2]], 16147; CHECK-NEXT: [[CONV12_2:%.*]] = trunc nuw i32 [[SHR_2]] to i16148; CHECK-NEXT: br label [[IF_END_2]]149; CHECK: if.end.2:150; CHECK-NEXT: [[STOREMERGE_2:%.*]] = phi i16 [ [[CONV28_2]], [[IF_ELSE_2]] ], [ [[CONV12_2]], [[IF_THEN_2]] ]151; CHECK-NEXT: store i16 [[STOREMERGE_2]], ptr [[ARRAYIDX_2]], align 2152; CHECK-NEXT: [[OR_238:%.*]] = or i16 [[OR_137]], [[STOREMERGE_2]]153; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 6154; CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 2155; CHECK-NEXT: [[CONV_3:%.*]] = sext i16 [[TMP42]] to i32156; CHECK-NEXT: [[CMP1_3:%.*]] = icmp sgt i16 [[TMP42]], 0157; CHECK-NEXT: [[ARRAYIDX4_3:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 6158; CHECK-NEXT: [[TMP43:%.*]] = load i16, ptr [[ARRAYIDX4_3]], align 2159; CHECK-NEXT: [[CONV5_3:%.*]] = zext i16 [[TMP43]] to i32160; CHECK-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 6161; CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX10_3]], align 2162; CHECK-NEXT: [[CONV11_3:%.*]] = zext i16 [[TMP44]] to i32163; CHECK-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]]164; CHECK: if.else.3:165; CHECK-NEXT: [[ADD21_3:%.*]] = sub nsw i32 [[CONV5_3]], [[CONV_3]]166; CHECK-NEXT: [[MUL25_3:%.*]] = mul i32 [[ADD21_3]], [[CONV11_3]]167; CHECK-NEXT: [[SHR26_3:%.*]] = lshr i32 [[MUL25_3]], 16168; CHECK-NEXT: [[TMP45:%.*]] = trunc nuw i32 [[SHR26_3]] to i16169; CHECK-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP45]]170; CHECK-NEXT: br label [[IF_END_3:%.*]]171; CHECK: if.then.3:172; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[CONV5_3]], [[CONV_3]]173; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[ADD_3]], [[CONV11_3]]174; CHECK-NEXT: [[SHR_3:%.*]] = lshr i32 [[MUL_3]], 16175; CHECK-NEXT: [[CONV12_3:%.*]] = trunc nuw i32 [[SHR_3]] to i16176; CHECK-NEXT: br label [[IF_END_3]]177; CHECK: if.end.3:178; CHECK-NEXT: [[STOREMERGE_3:%.*]] = phi i16 [ [[CONV28_3]], [[IF_ELSE_3]] ], [ [[CONV12_3]], [[IF_THEN_3]] ]179; CHECK-NEXT: store i16 [[STOREMERGE_3]], ptr [[ARRAYIDX_3]], align 2180; CHECK-NEXT: [[OR_339:%.*]] = or i16 [[OR_238]], [[STOREMERGE_3]]181; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 8182; CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2183; CHECK-NEXT: [[CONV_4:%.*]] = sext i16 [[TMP46]] to i32184; CHECK-NEXT: [[CMP1_4:%.*]] = icmp sgt i16 [[TMP46]], 0185; CHECK-NEXT: [[ARRAYIDX4_4:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 8186; CHECK-NEXT: [[TMP47:%.*]] = load i16, ptr [[ARRAYIDX4_4]], align 2187; CHECK-NEXT: [[CONV5_4:%.*]] = zext i16 [[TMP47]] to i32188; CHECK-NEXT: [[ARRAYIDX10_4:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 8189; CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[ARRAYIDX10_4]], align 2190; CHECK-NEXT: [[CONV11_4:%.*]] = zext i16 [[TMP48]] to i32191; CHECK-NEXT: br i1 [[CMP1_4]], label [[IF_THEN_4:%.*]], label [[IF_ELSE_4:%.*]]192; CHECK: if.else.4:193; CHECK-NEXT: [[ADD21_4:%.*]] = sub nsw i32 [[CONV5_4]], [[CONV_4]]194; CHECK-NEXT: [[MUL25_4:%.*]] = mul i32 [[ADD21_4]], [[CONV11_4]]195; CHECK-NEXT: [[SHR26_4:%.*]] = lshr i32 [[MUL25_4]], 16196; CHECK-NEXT: [[TMP49:%.*]] = trunc nuw i32 [[SHR26_4]] to i16197; CHECK-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP49]]198; CHECK-NEXT: br label [[IF_END_4:%.*]]199; CHECK: if.then.4:200; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[CONV5_4]], [[CONV_4]]201; CHECK-NEXT: [[MUL_4:%.*]] = mul i32 [[ADD_4]], [[CONV11_4]]202; CHECK-NEXT: [[SHR_4:%.*]] = lshr i32 [[MUL_4]], 16203; CHECK-NEXT: [[CONV12_4:%.*]] = trunc nuw i32 [[SHR_4]] to i16204; CHECK-NEXT: br label [[IF_END_4]]205; CHECK: if.end.4:206; CHECK-NEXT: [[STOREMERGE_4:%.*]] = phi i16 [ [[CONV28_4]], [[IF_ELSE_4]] ], [ [[CONV12_4]], [[IF_THEN_4]] ]207; CHECK-NEXT: store i16 [[STOREMERGE_4]], ptr [[ARRAYIDX_4]], align 2208; CHECK-NEXT: [[OR_440:%.*]] = or i16 [[OR_339]], [[STOREMERGE_4]]209; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 10210; CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2211; CHECK-NEXT: [[CONV_5:%.*]] = sext i16 [[TMP50]] to i32212; CHECK-NEXT: [[CMP1_5:%.*]] = icmp sgt i16 [[TMP50]], 0213; CHECK-NEXT: [[ARRAYIDX4_5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 10214; CHECK-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4_5]], align 2215; CHECK-NEXT: [[CONV5_5:%.*]] = zext i16 [[TMP51]] to i32216; CHECK-NEXT: [[ARRAYIDX10_5:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 10217; CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[ARRAYIDX10_5]], align 2218; CHECK-NEXT: [[CONV11_5:%.*]] = zext i16 [[TMP52]] to i32219; CHECK-NEXT: br i1 [[CMP1_5]], label [[IF_THEN_5:%.*]], label [[IF_ELSE_5:%.*]]220; CHECK: if.else.5:221; CHECK-NEXT: [[ADD21_5:%.*]] = sub nsw i32 [[CONV5_5]], [[CONV_5]]222; CHECK-NEXT: [[MUL25_5:%.*]] = mul i32 [[ADD21_5]], [[CONV11_5]]223; CHECK-NEXT: [[SHR26_5:%.*]] = lshr i32 [[MUL25_5]], 16224; CHECK-NEXT: [[TMP53:%.*]] = trunc nuw i32 [[SHR26_5]] to i16225; CHECK-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP53]]226; CHECK-NEXT: br label [[IF_END_5:%.*]]227; CHECK: if.then.5:228; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[CONV5_5]], [[CONV_5]]229; CHECK-NEXT: [[MUL_5:%.*]] = mul i32 [[ADD_5]], [[CONV11_5]]230; CHECK-NEXT: [[SHR_5:%.*]] = lshr i32 [[MUL_5]], 16231; CHECK-NEXT: [[CONV12_5:%.*]] = trunc nuw i32 [[SHR_5]] to i16232; CHECK-NEXT: br label [[IF_END_5]]233; CHECK: if.end.5:234; CHECK-NEXT: [[STOREMERGE_5:%.*]] = phi i16 [ [[CONV28_5]], [[IF_ELSE_5]] ], [ [[CONV12_5]], [[IF_THEN_5]] ]235; CHECK-NEXT: store i16 [[STOREMERGE_5]], ptr [[ARRAYIDX_5]], align 2236; CHECK-NEXT: [[OR_541:%.*]] = or i16 [[OR_440]], [[STOREMERGE_5]]237; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 12238; CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2239; CHECK-NEXT: [[CONV_6:%.*]] = sext i16 [[TMP54]] to i32240; CHECK-NEXT: [[CMP1_6:%.*]] = icmp sgt i16 [[TMP54]], 0241; CHECK-NEXT: [[ARRAYIDX4_6:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 12242; CHECK-NEXT: [[TMP55:%.*]] = load i16, ptr [[ARRAYIDX4_6]], align 2243; CHECK-NEXT: [[CONV5_6:%.*]] = zext i16 [[TMP55]] to i32244; CHECK-NEXT: [[ARRAYIDX10_6:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 12245; CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[ARRAYIDX10_6]], align 2246; CHECK-NEXT: [[CONV11_6:%.*]] = zext i16 [[TMP56]] to i32247; CHECK-NEXT: br i1 [[CMP1_6]], label [[IF_THEN_6:%.*]], label [[IF_ELSE_6:%.*]]248; CHECK: if.else.6:249; CHECK-NEXT: [[ADD21_6:%.*]] = sub nsw i32 [[CONV5_6]], [[CONV_6]]250; CHECK-NEXT: [[MUL25_6:%.*]] = mul i32 [[ADD21_6]], [[CONV11_6]]251; CHECK-NEXT: [[SHR26_6:%.*]] = lshr i32 [[MUL25_6]], 16252; CHECK-NEXT: [[TMP57:%.*]] = trunc nuw i32 [[SHR26_6]] to i16253; CHECK-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP57]]254; CHECK-NEXT: br label [[IF_END_6:%.*]]255; CHECK: if.then.6:256; CHECK-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[CONV5_6]], [[CONV_6]]257; CHECK-NEXT: [[MUL_6:%.*]] = mul i32 [[ADD_6]], [[CONV11_6]]258; CHECK-NEXT: [[SHR_6:%.*]] = lshr i32 [[MUL_6]], 16259; CHECK-NEXT: [[CONV12_6:%.*]] = trunc nuw i32 [[SHR_6]] to i16260; CHECK-NEXT: br label [[IF_END_6]]261; CHECK: if.end.6:262; CHECK-NEXT: [[STOREMERGE_6:%.*]] = phi i16 [ [[CONV28_6]], [[IF_ELSE_6]] ], [ [[CONV12_6]], [[IF_THEN_6]] ]263; CHECK-NEXT: store i16 [[STOREMERGE_6]], ptr [[ARRAYIDX_6]], align 2264; CHECK-NEXT: [[OR_642:%.*]] = or i16 [[OR_541]], [[STOREMERGE_6]]265; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 14266; CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2267; CHECK-NEXT: [[CONV_7:%.*]] = sext i16 [[TMP58]] to i32268; CHECK-NEXT: [[CMP1_7:%.*]] = icmp sgt i16 [[TMP58]], 0269; CHECK-NEXT: [[ARRAYIDX4_7:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 14270; CHECK-NEXT: [[TMP59:%.*]] = load i16, ptr [[ARRAYIDX4_7]], align 2271; CHECK-NEXT: [[CONV5_7:%.*]] = zext i16 [[TMP59]] to i32272; CHECK-NEXT: [[ARRAYIDX10_7:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 14273; CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[ARRAYIDX10_7]], align 2274; CHECK-NEXT: [[CONV11_7:%.*]] = zext i16 [[TMP60]] to i32275; CHECK-NEXT: br i1 [[CMP1_7]], label [[IF_THEN_7:%.*]], label [[IF_ELSE_7:%.*]]276; CHECK: if.else.7:277; CHECK-NEXT: [[ADD21_7:%.*]] = sub nsw i32 [[CONV5_7]], [[CONV_7]]278; CHECK-NEXT: [[MUL25_7:%.*]] = mul i32 [[ADD21_7]], [[CONV11_7]]279; CHECK-NEXT: [[SHR26_7:%.*]] = lshr i32 [[MUL25_7]], 16280; CHECK-NEXT: [[TMP61:%.*]] = trunc nuw i32 [[SHR26_7]] to i16281; CHECK-NEXT: [[CONV28_7:%.*]] = sub i16 0, [[TMP61]]282; CHECK-NEXT: br label [[IF_END_7:%.*]]283; CHECK: if.then.7:284; CHECK-NEXT: [[ADD_7:%.*]] = add nuw nsw i32 [[CONV5_7]], [[CONV_7]]285; CHECK-NEXT: [[MUL_7:%.*]] = mul i32 [[ADD_7]], [[CONV11_7]]286; CHECK-NEXT: [[SHR_7:%.*]] = lshr i32 [[MUL_7]], 16287; CHECK-NEXT: [[CONV12_7:%.*]] = trunc nuw i32 [[SHR_7]] to i16288; CHECK-NEXT: br label [[IF_END_7]]289; CHECK: if.end.7:290; CHECK-NEXT: [[STOREMERGE_7:%.*]] = phi i16 [ [[CONV28_7]], [[IF_ELSE_7]] ], [ [[CONV12_7]], [[IF_THEN_7]] ]291; CHECK-NEXT: store i16 [[STOREMERGE_7]], ptr [[ARRAYIDX_7]], align 2292; CHECK-NEXT: [[OR_743:%.*]] = or i16 [[OR_642]], [[STOREMERGE_7]]293; CHECK-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 16294; CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[ARRAYIDX_8]], align 2295; CHECK-NEXT: [[CONV_8:%.*]] = sext i16 [[TMP62]] to i32296; CHECK-NEXT: [[CMP1_8:%.*]] = icmp sgt i16 [[TMP62]], 0297; CHECK-NEXT: [[ARRAYIDX4_8:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 16298; CHECK-NEXT: [[TMP63:%.*]] = load i16, ptr [[ARRAYIDX4_8]], align 2299; CHECK-NEXT: [[CONV5_8:%.*]] = zext i16 [[TMP63]] to i32300; CHECK-NEXT: [[ARRAYIDX10_8:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 16301; CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[ARRAYIDX10_8]], align 2302; CHECK-NEXT: [[CONV11_8:%.*]] = zext i16 [[TMP64]] to i32303; CHECK-NEXT: br i1 [[CMP1_8]], label [[IF_THEN_8:%.*]], label [[IF_ELSE_8:%.*]]304; CHECK: if.else.8:305; CHECK-NEXT: [[ADD21_8:%.*]] = sub nsw i32 [[CONV5_8]], [[CONV_8]]306; CHECK-NEXT: [[MUL25_8:%.*]] = mul i32 [[ADD21_8]], [[CONV11_8]]307; CHECK-NEXT: [[SHR26_8:%.*]] = lshr i32 [[MUL25_8]], 16308; CHECK-NEXT: [[TMP65:%.*]] = trunc nuw i32 [[SHR26_8]] to i16309; CHECK-NEXT: [[CONV28_8:%.*]] = sub i16 0, [[TMP65]]310; CHECK-NEXT: br label [[IF_END_8:%.*]]311; CHECK: if.then.8:312; CHECK-NEXT: [[ADD_8:%.*]] = add nuw nsw i32 [[CONV5_8]], [[CONV_8]]313; CHECK-NEXT: [[MUL_8:%.*]] = mul i32 [[ADD_8]], [[CONV11_8]]314; CHECK-NEXT: [[SHR_8:%.*]] = lshr i32 [[MUL_8]], 16315; CHECK-NEXT: [[CONV12_8:%.*]] = trunc nuw i32 [[SHR_8]] to i16316; CHECK-NEXT: br label [[IF_END_8]]317; CHECK: if.end.8:318; CHECK-NEXT: [[STOREMERGE_8:%.*]] = phi i16 [ [[CONV28_8]], [[IF_ELSE_8]] ], [ [[CONV12_8]], [[IF_THEN_8]] ]319; CHECK-NEXT: store i16 [[STOREMERGE_8]], ptr [[ARRAYIDX_8]], align 2320; CHECK-NEXT: [[OR_844:%.*]] = or i16 [[OR_743]], [[STOREMERGE_8]]321; CHECK-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 18322; CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[ARRAYIDX_9]], align 2323; CHECK-NEXT: [[CONV_9:%.*]] = sext i16 [[TMP66]] to i32324; CHECK-NEXT: [[CMP1_9:%.*]] = icmp sgt i16 [[TMP66]], 0325; CHECK-NEXT: [[ARRAYIDX4_9:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 18326; CHECK-NEXT: [[TMP67:%.*]] = load i16, ptr [[ARRAYIDX4_9]], align 2327; CHECK-NEXT: [[CONV5_9:%.*]] = zext i16 [[TMP67]] to i32328; CHECK-NEXT: [[ARRAYIDX10_9:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 18329; CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[ARRAYIDX10_9]], align 2330; CHECK-NEXT: [[CONV11_9:%.*]] = zext i16 [[TMP68]] to i32331; CHECK-NEXT: br i1 [[CMP1_9]], label [[IF_THEN_9:%.*]], label [[IF_ELSE_9:%.*]]332; CHECK: if.else.9:333; CHECK-NEXT: [[ADD21_9:%.*]] = sub nsw i32 [[CONV5_9]], [[CONV_9]]334; CHECK-NEXT: [[MUL25_9:%.*]] = mul i32 [[ADD21_9]], [[CONV11_9]]335; CHECK-NEXT: [[SHR26_9:%.*]] = lshr i32 [[MUL25_9]], 16336; CHECK-NEXT: [[TMP69:%.*]] = trunc nuw i32 [[SHR26_9]] to i16337; CHECK-NEXT: [[CONV28_9:%.*]] = sub i16 0, [[TMP69]]338; CHECK-NEXT: br label [[IF_END_9:%.*]]339; CHECK: if.then.9:340; CHECK-NEXT: [[ADD_9:%.*]] = add nuw nsw i32 [[CONV5_9]], [[CONV_9]]341; CHECK-NEXT: [[MUL_9:%.*]] = mul i32 [[ADD_9]], [[CONV11_9]]342; CHECK-NEXT: [[SHR_9:%.*]] = lshr i32 [[MUL_9]], 16343; CHECK-NEXT: [[CONV12_9:%.*]] = trunc nuw i32 [[SHR_9]] to i16344; CHECK-NEXT: br label [[IF_END_9]]345; CHECK: if.end.9:346; CHECK-NEXT: [[STOREMERGE_9:%.*]] = phi i16 [ [[CONV28_9]], [[IF_ELSE_9]] ], [ [[CONV12_9]], [[IF_THEN_9]] ]347; CHECK-NEXT: store i16 [[STOREMERGE_9]], ptr [[ARRAYIDX_9]], align 2348; CHECK-NEXT: [[OR_945:%.*]] = or i16 [[OR_844]], [[STOREMERGE_9]]349; CHECK-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 20350; CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[ARRAYIDX_10]], align 2351; CHECK-NEXT: [[CONV_10:%.*]] = sext i16 [[TMP70]] to i32352; CHECK-NEXT: [[CMP1_10:%.*]] = icmp sgt i16 [[TMP70]], 0353; CHECK-NEXT: [[ARRAYIDX4_10:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 20354; CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[ARRAYIDX4_10]], align 2355; CHECK-NEXT: [[CONV5_10:%.*]] = zext i16 [[TMP71]] to i32356; CHECK-NEXT: [[ARRAYIDX10_10:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 20357; CHECK-NEXT: [[TMP72:%.*]] = load i16, ptr [[ARRAYIDX10_10]], align 2358; CHECK-NEXT: [[CONV11_10:%.*]] = zext i16 [[TMP72]] to i32359; CHECK-NEXT: br i1 [[CMP1_10]], label [[IF_THEN_10:%.*]], label [[IF_ELSE_10:%.*]]360; CHECK: if.else.10:361; CHECK-NEXT: [[ADD21_10:%.*]] = sub nsw i32 [[CONV5_10]], [[CONV_10]]362; CHECK-NEXT: [[MUL25_10:%.*]] = mul i32 [[ADD21_10]], [[CONV11_10]]363; CHECK-NEXT: [[SHR26_10:%.*]] = lshr i32 [[MUL25_10]], 16364; CHECK-NEXT: [[TMP73:%.*]] = trunc nuw i32 [[SHR26_10]] to i16365; CHECK-NEXT: [[CONV28_10:%.*]] = sub i16 0, [[TMP73]]366; CHECK-NEXT: br label [[IF_END_10:%.*]]367; CHECK: if.then.10:368; CHECK-NEXT: [[ADD_10:%.*]] = add nuw nsw i32 [[CONV5_10]], [[CONV_10]]369; CHECK-NEXT: [[MUL_10:%.*]] = mul i32 [[ADD_10]], [[CONV11_10]]370; CHECK-NEXT: [[SHR_10:%.*]] = lshr i32 [[MUL_10]], 16371; CHECK-NEXT: [[CONV12_10:%.*]] = trunc nuw i32 [[SHR_10]] to i16372; CHECK-NEXT: br label [[IF_END_10]]373; CHECK: if.end.10:374; CHECK-NEXT: [[STOREMERGE_10:%.*]] = phi i16 [ [[CONV28_10]], [[IF_ELSE_10]] ], [ [[CONV12_10]], [[IF_THEN_10]] ]375; CHECK-NEXT: store i16 [[STOREMERGE_10]], ptr [[ARRAYIDX_10]], align 2376; CHECK-NEXT: [[OR_1046:%.*]] = or i16 [[OR_945]], [[STOREMERGE_10]]377; CHECK-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 22378; CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[ARRAYIDX_11]], align 2379; CHECK-NEXT: [[CONV_11:%.*]] = sext i16 [[TMP74]] to i32380; CHECK-NEXT: [[CMP1_11:%.*]] = icmp sgt i16 [[TMP74]], 0381; CHECK-NEXT: [[ARRAYIDX4_11:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 22382; CHECK-NEXT: [[TMP75:%.*]] = load i16, ptr [[ARRAYIDX4_11]], align 2383; CHECK-NEXT: [[CONV5_11:%.*]] = zext i16 [[TMP75]] to i32384; CHECK-NEXT: [[ARRAYIDX10_11:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 22385; CHECK-NEXT: [[TMP76:%.*]] = load i16, ptr [[ARRAYIDX10_11]], align 2386; CHECK-NEXT: [[CONV11_11:%.*]] = zext i16 [[TMP76]] to i32387; CHECK-NEXT: br i1 [[CMP1_11]], label [[IF_THEN_11:%.*]], label [[IF_ELSE_11:%.*]]388; CHECK: if.else.11:389; CHECK-NEXT: [[ADD21_11:%.*]] = sub nsw i32 [[CONV5_11]], [[CONV_11]]390; CHECK-NEXT: [[MUL25_11:%.*]] = mul i32 [[ADD21_11]], [[CONV11_11]]391; CHECK-NEXT: [[SHR26_11:%.*]] = lshr i32 [[MUL25_11]], 16392; CHECK-NEXT: [[TMP77:%.*]] = trunc nuw i32 [[SHR26_11]] to i16393; CHECK-NEXT: [[CONV28_11:%.*]] = sub i16 0, [[TMP77]]394; CHECK-NEXT: br label [[IF_END_11:%.*]]395; CHECK: if.then.11:396; CHECK-NEXT: [[ADD_11:%.*]] = add nuw nsw i32 [[CONV5_11]], [[CONV_11]]397; CHECK-NEXT: [[MUL_11:%.*]] = mul i32 [[ADD_11]], [[CONV11_11]]398; CHECK-NEXT: [[SHR_11:%.*]] = lshr i32 [[MUL_11]], 16399; CHECK-NEXT: [[CONV12_11:%.*]] = trunc nuw i32 [[SHR_11]] to i16400; CHECK-NEXT: br label [[IF_END_11]]401; CHECK: if.end.11:402; CHECK-NEXT: [[STOREMERGE_11:%.*]] = phi i16 [ [[CONV28_11]], [[IF_ELSE_11]] ], [ [[CONV12_11]], [[IF_THEN_11]] ]403; CHECK-NEXT: store i16 [[STOREMERGE_11]], ptr [[ARRAYIDX_11]], align 2404; CHECK-NEXT: [[OR_1147:%.*]] = or i16 [[OR_1046]], [[STOREMERGE_11]]405; CHECK-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 24406; CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[ARRAYIDX_12]], align 2407; CHECK-NEXT: [[CONV_12:%.*]] = sext i16 [[TMP78]] to i32408; CHECK-NEXT: [[CMP1_12:%.*]] = icmp sgt i16 [[TMP78]], 0409; CHECK-NEXT: [[ARRAYIDX4_12:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 24410; CHECK-NEXT: [[TMP79:%.*]] = load i16, ptr [[ARRAYIDX4_12]], align 2411; CHECK-NEXT: [[CONV5_12:%.*]] = zext i16 [[TMP79]] to i32412; CHECK-NEXT: [[ARRAYIDX10_12:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 24413; CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[ARRAYIDX10_12]], align 2414; CHECK-NEXT: [[CONV11_12:%.*]] = zext i16 [[TMP80]] to i32415; CHECK-NEXT: br i1 [[CMP1_12]], label [[IF_THEN_12:%.*]], label [[IF_ELSE_12:%.*]]416; CHECK: if.else.12:417; CHECK-NEXT: [[ADD21_12:%.*]] = sub nsw i32 [[CONV5_12]], [[CONV_12]]418; CHECK-NEXT: [[MUL25_12:%.*]] = mul i32 [[ADD21_12]], [[CONV11_12]]419; CHECK-NEXT: [[SHR26_12:%.*]] = lshr i32 [[MUL25_12]], 16420; CHECK-NEXT: [[TMP81:%.*]] = trunc nuw i32 [[SHR26_12]] to i16421; CHECK-NEXT: [[CONV28_12:%.*]] = sub i16 0, [[TMP81]]422; CHECK-NEXT: br label [[IF_END_12:%.*]]423; CHECK: if.then.12:424; CHECK-NEXT: [[ADD_12:%.*]] = add nuw nsw i32 [[CONV5_12]], [[CONV_12]]425; CHECK-NEXT: [[MUL_12:%.*]] = mul i32 [[ADD_12]], [[CONV11_12]]426; CHECK-NEXT: [[SHR_12:%.*]] = lshr i32 [[MUL_12]], 16427; CHECK-NEXT: [[CONV12_12:%.*]] = trunc nuw i32 [[SHR_12]] to i16428; CHECK-NEXT: br label [[IF_END_12]]429; CHECK: if.end.12:430; CHECK-NEXT: [[STOREMERGE_12:%.*]] = phi i16 [ [[CONV28_12]], [[IF_ELSE_12]] ], [ [[CONV12_12]], [[IF_THEN_12]] ]431; CHECK-NEXT: store i16 [[STOREMERGE_12]], ptr [[ARRAYIDX_12]], align 2432; CHECK-NEXT: [[OR_1248:%.*]] = or i16 [[OR_1147]], [[STOREMERGE_12]]433; CHECK-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 26434; CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[ARRAYIDX_13]], align 2435; CHECK-NEXT: [[CONV_13:%.*]] = sext i16 [[TMP82]] to i32436; CHECK-NEXT: [[CMP1_13:%.*]] = icmp sgt i16 [[TMP82]], 0437; CHECK-NEXT: [[ARRAYIDX4_13:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 26438; CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[ARRAYIDX4_13]], align 2439; CHECK-NEXT: [[CONV5_13:%.*]] = zext i16 [[TMP83]] to i32440; CHECK-NEXT: [[ARRAYIDX10_13:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 26441; CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[ARRAYIDX10_13]], align 2442; CHECK-NEXT: [[CONV11_13:%.*]] = zext i16 [[TMP84]] to i32443; CHECK-NEXT: br i1 [[CMP1_13]], label [[IF_THEN_13:%.*]], label [[IF_ELSE_13:%.*]]444; CHECK: if.else.13:445; CHECK-NEXT: [[ADD21_13:%.*]] = sub nsw i32 [[CONV5_13]], [[CONV_13]]446; CHECK-NEXT: [[MUL25_13:%.*]] = mul i32 [[ADD21_13]], [[CONV11_13]]447; CHECK-NEXT: [[SHR26_13:%.*]] = lshr i32 [[MUL25_13]], 16448; CHECK-NEXT: [[TMP85:%.*]] = trunc nuw i32 [[SHR26_13]] to i16449; CHECK-NEXT: [[CONV28_13:%.*]] = sub i16 0, [[TMP85]]450; CHECK-NEXT: br label [[IF_END_13:%.*]]451; CHECK: if.then.13:452; CHECK-NEXT: [[ADD_13:%.*]] = add nuw nsw i32 [[CONV5_13]], [[CONV_13]]453; CHECK-NEXT: [[MUL_13:%.*]] = mul i32 [[ADD_13]], [[CONV11_13]]454; CHECK-NEXT: [[SHR_13:%.*]] = lshr i32 [[MUL_13]], 16455; CHECK-NEXT: [[CONV12_13:%.*]] = trunc nuw i32 [[SHR_13]] to i16456; CHECK-NEXT: br label [[IF_END_13]]457; CHECK: if.end.13:458; CHECK-NEXT: [[STOREMERGE_13:%.*]] = phi i16 [ [[CONV28_13]], [[IF_ELSE_13]] ], [ [[CONV12_13]], [[IF_THEN_13]] ]459; CHECK-NEXT: store i16 [[STOREMERGE_13]], ptr [[ARRAYIDX_13]], align 2460; CHECK-NEXT: [[OR_1349:%.*]] = or i16 [[OR_1248]], [[STOREMERGE_13]]461; CHECK-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 28462; CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[ARRAYIDX_14]], align 2463; CHECK-NEXT: [[CONV_14:%.*]] = sext i16 [[TMP86]] to i32464; CHECK-NEXT: [[CMP1_14:%.*]] = icmp sgt i16 [[TMP86]], 0465; CHECK-NEXT: [[ARRAYIDX4_14:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 28466; CHECK-NEXT: [[TMP87:%.*]] = load i16, ptr [[ARRAYIDX4_14]], align 2467; CHECK-NEXT: [[CONV5_14:%.*]] = zext i16 [[TMP87]] to i32468; CHECK-NEXT: [[ARRAYIDX10_14:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 28469; CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[ARRAYIDX10_14]], align 2470; CHECK-NEXT: [[CONV11_14:%.*]] = zext i16 [[TMP88]] to i32471; CHECK-NEXT: br i1 [[CMP1_14]], label [[IF_THEN_14:%.*]], label [[IF_ELSE_14:%.*]]472; CHECK: if.else.14:473; CHECK-NEXT: [[ADD21_14:%.*]] = sub nsw i32 [[CONV5_14]], [[CONV_14]]474; CHECK-NEXT: [[MUL25_14:%.*]] = mul i32 [[ADD21_14]], [[CONV11_14]]475; CHECK-NEXT: [[SHR26_14:%.*]] = lshr i32 [[MUL25_14]], 16476; CHECK-NEXT: [[TMP89:%.*]] = trunc nuw i32 [[SHR26_14]] to i16477; CHECK-NEXT: [[CONV28_14:%.*]] = sub i16 0, [[TMP89]]478; CHECK-NEXT: br label [[IF_END_14:%.*]]479; CHECK: if.then.14:480; CHECK-NEXT: [[ADD_14:%.*]] = add nuw nsw i32 [[CONV5_14]], [[CONV_14]]481; CHECK-NEXT: [[MUL_14:%.*]] = mul i32 [[ADD_14]], [[CONV11_14]]482; CHECK-NEXT: [[SHR_14:%.*]] = lshr i32 [[MUL_14]], 16483; CHECK-NEXT: [[CONV12_14:%.*]] = trunc nuw i32 [[SHR_14]] to i16484; CHECK-NEXT: br label [[IF_END_14]]485; CHECK: if.end.14:486; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i16 [ [[CONV28_14]], [[IF_ELSE_14]] ], [ [[CONV12_14]], [[IF_THEN_14]] ]487; CHECK-NEXT: store i16 [[STOREMERGE_14]], ptr [[ARRAYIDX_14]], align 2488; CHECK-NEXT: [[OR_1450:%.*]] = or i16 [[OR_1349]], [[STOREMERGE_14]]489; CHECK-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 30490; CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[ARRAYIDX_15]], align 2491; CHECK-NEXT: [[CONV_15:%.*]] = sext i16 [[TMP90]] to i32492; CHECK-NEXT: [[CMP1_15:%.*]] = icmp sgt i16 [[TMP90]], 0493; CHECK-NEXT: [[ARRAYIDX4_15:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 30494; CHECK-NEXT: [[TMP91:%.*]] = load i16, ptr [[ARRAYIDX4_15]], align 2495; CHECK-NEXT: [[CONV5_15:%.*]] = zext i16 [[TMP91]] to i32496; CHECK-NEXT: [[ARRAYIDX10_15:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 30497; CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[ARRAYIDX10_15]], align 2498; CHECK-NEXT: [[CONV11_15:%.*]] = zext i16 [[TMP92]] to i32499; CHECK-NEXT: br i1 [[CMP1_15]], label [[IF_THEN_15:%.*]], label [[IF_ELSE_15:%.*]]500; CHECK: if.else.15:501; CHECK-NEXT: [[ADD21_15:%.*]] = sub nsw i32 [[CONV5_15]], [[CONV_15]]502; CHECK-NEXT: [[MUL25_15:%.*]] = mul i32 [[ADD21_15]], [[CONV11_15]]503; CHECK-NEXT: [[SHR26_15:%.*]] = lshr i32 [[MUL25_15]], 16504; CHECK-NEXT: [[TMP93:%.*]] = trunc nuw i32 [[SHR26_15]] to i16505; CHECK-NEXT: [[CONV28_15:%.*]] = sub i16 0, [[TMP93]]506; CHECK-NEXT: br label [[IF_END_15]]507; CHECK: if.then.15:508; CHECK-NEXT: [[ADD_15:%.*]] = add nuw nsw i32 [[CONV5_15]], [[CONV_15]]509; CHECK-NEXT: [[MUL_15:%.*]] = mul i32 [[ADD_15]], [[CONV11_15]]510; CHECK-NEXT: [[SHR_15:%.*]] = lshr i32 [[MUL_15]], 16511; CHECK-NEXT: [[CONV12_15:%.*]] = trunc nuw i32 [[SHR_15]] to i16512; CHECK-NEXT: br label [[IF_END_15]]513; CHECK: if.end.15:514; CHECK-NEXT: [[STOREMERGE_15:%.*]] = phi i16 [ [[CONV28_15]], [[IF_ELSE_15]] ], [ [[CONV12_15]], [[IF_THEN_15]] ]515; CHECK-NEXT: store i16 [[STOREMERGE_15]], ptr [[ARRAYIDX_15]], align 2516; CHECK-NEXT: [[OR_1551]] = or i16 [[OR_1450]], [[STOREMERGE_15]]517; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]518;519entry:520 %dct.addr = alloca ptr, align 8521 %mf.addr = alloca ptr, align 8522 %bias.addr = alloca ptr, align 8523 %nz = alloca i32, align 4524 %i = alloca i32, align 4525 store ptr %dct, ptr %dct.addr, align 8526 store ptr %mf, ptr %mf.addr, align 8527 store ptr %bias, ptr %bias.addr, align 8528 call void @llvm.lifetime.start.p0(ptr %nz) #2529 store i32 0, ptr %nz, align 4530 call void @llvm.lifetime.start.p0(ptr %i) #2531 store i32 0, ptr %i, align 4532 br label %for.cond533 534for.cond: ; preds = %for.inc, %entry535 %0 = load i32, ptr %i, align 4536 %cmp = icmp slt i32 %0, 16537 br i1 %cmp, label %for.body, label %for.cond.cleanup538 539for.cond.cleanup: ; preds = %for.cond540 call void @llvm.lifetime.end.p0(ptr %i) #2541 br label %for.end542 543for.body: ; preds = %for.cond544 %1 = load ptr, ptr %dct.addr, align 8545 %2 = load i32, ptr %i, align 4546 %idxprom = sext i32 %2 to i64547 %arrayidx = getelementptr inbounds i16, ptr %1, i64 %idxprom548 %3 = load i16, ptr %arrayidx, align 2549 %conv = sext i16 %3 to i32550 %cmp1 = icmp sgt i32 %conv, 0551 br i1 %cmp1, label %if.then, label %if.else552 553if.then: ; preds = %for.body554 %4 = load ptr, ptr %bias.addr, align 8555 %5 = load i32, ptr %i, align 4556 %idxprom3 = sext i32 %5 to i64557 %arrayidx4 = getelementptr inbounds i16, ptr %4, i64 %idxprom3558 %6 = load i16, ptr %arrayidx4, align 2559 %conv5 = zext i16 %6 to i32560 %7 = load ptr, ptr %dct.addr, align 8561 %8 = load i32, ptr %i, align 4562 %idxprom6 = sext i32 %8 to i64563 %arrayidx7 = getelementptr inbounds i16, ptr %7, i64 %idxprom6564 %9 = load i16, ptr %arrayidx7, align 2565 %conv8 = sext i16 %9 to i32566 %add = add i32 %conv5, %conv8567 %10 = load ptr, ptr %mf.addr, align 8568 %11 = load i32, ptr %i, align 4569 %idxprom9 = sext i32 %11 to i64570 %arrayidx10 = getelementptr inbounds i16, ptr %10, i64 %idxprom9571 %12 = load i16, ptr %arrayidx10, align 2572 %conv11 = zext i16 %12 to i32573 %mul = mul i32 %add, %conv11574 %shr = lshr i32 %mul, 16575 %conv12 = trunc i32 %shr to i16576 %13 = load ptr, ptr %dct.addr, align 8577 %14 = load i32, ptr %i, align 4578 %idxprom13 = sext i32 %14 to i64579 %arrayidx14 = getelementptr inbounds i16, ptr %13, i64 %idxprom13580 store i16 %conv12, ptr %arrayidx14, align 2581 br label %if.end582 583if.else: ; preds = %for.body584 %15 = load ptr, ptr %bias.addr, align 8585 %16 = load i32, ptr %i, align 4586 %idxprom15 = sext i32 %16 to i64587 %arrayidx16 = getelementptr inbounds i16, ptr %15, i64 %idxprom15588 %17 = load i16, ptr %arrayidx16, align 2589 %conv17 = zext i16 %17 to i32590 %18 = load ptr, ptr %dct.addr, align 8591 %19 = load i32, ptr %i, align 4592 %idxprom18 = sext i32 %19 to i64593 %arrayidx19 = getelementptr inbounds i16, ptr %18, i64 %idxprom18594 %20 = load i16, ptr %arrayidx19, align 2595 %conv20 = sext i16 %20 to i32596 %sub = sub nsw i32 0, %conv20597 %add21 = add i32 %conv17, %sub598 %21 = load ptr, ptr %mf.addr, align 8599 %22 = load i32, ptr %i, align 4600 %idxprom22 = sext i32 %22 to i64601 %arrayidx23 = getelementptr inbounds i16, ptr %21, i64 %idxprom22602 %23 = load i16, ptr %arrayidx23, align 2603 %conv24 = zext i16 %23 to i32604 %mul25 = mul i32 %add21, %conv24605 %shr26 = lshr i32 %mul25, 16606 %sub27 = sub nsw i32 0, %shr26607 %conv28 = trunc i32 %sub27 to i16608 %24 = load ptr, ptr %dct.addr, align 8609 %25 = load i32, ptr %i, align 4610 %idxprom29 = sext i32 %25 to i64611 %arrayidx30 = getelementptr inbounds i16, ptr %24, i64 %idxprom29612 store i16 %conv28, ptr %arrayidx30, align 2613 br label %if.end614 615if.end: ; preds = %if.else, %if.then616 %26 = load ptr, ptr %dct.addr, align 8617 %27 = load i32, ptr %i, align 4618 %idxprom31 = sext i32 %27 to i64619 %arrayidx32 = getelementptr inbounds i16, ptr %26, i64 %idxprom31620 %28 = load i16, ptr %arrayidx32, align 2621 %conv33 = sext i16 %28 to i32622 %29 = load i32, ptr %nz, align 4623 %or = or i32 %29, %conv33624 store i32 %or, ptr %nz, align 4625 br label %for.inc626 627for.inc: ; preds = %if.end628 %30 = load i32, ptr %i, align 4629 %inc = add nsw i32 %30, 1630 store i32 %inc, ptr %i, align 4631 br label %for.cond632 633for.end: ; preds = %for.cond.cleanup634 %31 = load i32, ptr %nz, align 4635 %tobool = icmp ne i32 %31, 0636 %lnot = xor i1 %tobool, true637 %lnot34 = xor i1 %lnot, true638 %lnot.ext = zext i1 %lnot34 to i32639 call void @llvm.lifetime.end.p0(ptr %nz) #2640 ret i32 %lnot.ext641}642 643; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)644declare void @llvm.lifetime.start.p0(ptr nocapture) #1645 646; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)647declare void @llvm.lifetime.end.p0(ptr nocapture) #1648 649