500 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S -O3 < %s | FileCheck %s --check-prefixes=CHECK-O33; RUN: opt -S -passes="default<O3>,default<O3>" < %s | FileCheck %s --check-prefixes=CHECK-LTO4 5target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"6target triple = "aarch64"7 8define dso_local i32 @test(ptr noundef %p1, i32 noundef %s_p1, ptr noundef %p2, i32 noundef %s_p2) #0 {9; CHECK-O3-LABEL: define dso_local i32 @test(10; CHECK-O3-SAME: ptr noundef readonly captures(none) [[P1:%.*]], i32 noundef [[S_P1:%.*]], ptr noundef readonly captures(none) [[P2:%.*]], i32 noundef [[S_P2:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {11; CHECK-O3-NEXT: [[ENTRY:.*:]]12; CHECK-O3-NEXT: [[IDX_EXT8:%.*]] = sext i32 [[S_P2]] to i6413; CHECK-O3-NEXT: [[IDX_EXT:%.*]] = sext i32 [[S_P1]] to i6414; CHECK-O3-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[P1]], align 1, !tbaa [[CHAR_TBAA0:![0-9]+]]15; CHECK-O3-NEXT: [[TMP1:%.*]] = zext <16 x i8> [[TMP0]] to <16 x i16>16; CHECK-O3-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[P2]], align 1, !tbaa [[CHAR_TBAA0]]17; CHECK-O3-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[TMP2]] to <16 x i16>18; CHECK-O3-NEXT: [[TMP4:%.*]] = sub nsw <16 x i16> [[TMP1]], [[TMP3]]19; CHECK-O3-NEXT: [[TMP5:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP4]], i1 false)20; CHECK-O3-NEXT: [[TMP6:%.*]] = zext <16 x i16> [[TMP5]] to <16 x i32>21; CHECK-O3-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP6]])22; CHECK-O3-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IDX_EXT]]23; CHECK-O3-NEXT: [[ADD_PTR9:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IDX_EXT8]]24; CHECK-O3-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[ADD_PTR]], align 1, !tbaa [[CHAR_TBAA0]]25; CHECK-O3-NEXT: [[TMP9:%.*]] = zext <16 x i8> [[TMP8]] to <16 x i16>26; CHECK-O3-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[ADD_PTR9]], align 1, !tbaa [[CHAR_TBAA0]]27; CHECK-O3-NEXT: [[TMP11:%.*]] = zext <16 x i8> [[TMP10]] to <16 x i16>28; CHECK-O3-NEXT: [[TMP12:%.*]] = sub nsw <16 x i16> [[TMP9]], [[TMP11]]29; CHECK-O3-NEXT: [[TMP13:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP12]], i1 false)30; CHECK-O3-NEXT: [[TMP14:%.*]] = zext <16 x i16> [[TMP13]] to <16 x i32>31; CHECK-O3-NEXT: [[TMP15:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP14]])32; CHECK-O3-NEXT: [[OP_RDX_1:%.*]] = add i32 [[TMP15]], [[TMP7]]33; CHECK-O3-NEXT: [[ADD_PTR_1:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]34; CHECK-O3-NEXT: [[ADD_PTR9_1:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9]], i64 [[IDX_EXT8]]35; CHECK-O3-NEXT: [[TMP16:%.*]] = load <16 x i8>, ptr [[ADD_PTR_1]], align 1, !tbaa [[CHAR_TBAA0]]36; CHECK-O3-NEXT: [[TMP17:%.*]] = zext <16 x i8> [[TMP16]] to <16 x i16>37; CHECK-O3-NEXT: [[TMP18:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_1]], align 1, !tbaa [[CHAR_TBAA0]]38; CHECK-O3-NEXT: [[TMP19:%.*]] = zext <16 x i8> [[TMP18]] to <16 x i16>39; CHECK-O3-NEXT: [[TMP20:%.*]] = sub nsw <16 x i16> [[TMP17]], [[TMP19]]40; CHECK-O3-NEXT: [[TMP21:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP20]], i1 false)41; CHECK-O3-NEXT: [[TMP22:%.*]] = zext <16 x i16> [[TMP21]] to <16 x i32>42; CHECK-O3-NEXT: [[TMP23:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP22]])43; CHECK-O3-NEXT: [[OP_RDX_2:%.*]] = add i32 [[TMP23]], [[OP_RDX_1]]44; CHECK-O3-NEXT: [[ADD_PTR_2:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_1]], i64 [[IDX_EXT]]45; CHECK-O3-NEXT: [[ADD_PTR9_2:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_1]], i64 [[IDX_EXT8]]46; CHECK-O3-NEXT: [[TMP24:%.*]] = load <16 x i8>, ptr [[ADD_PTR_2]], align 1, !tbaa [[CHAR_TBAA0]]47; CHECK-O3-NEXT: [[TMP25:%.*]] = zext <16 x i8> [[TMP24]] to <16 x i16>48; CHECK-O3-NEXT: [[TMP26:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_2]], align 1, !tbaa [[CHAR_TBAA0]]49; CHECK-O3-NEXT: [[TMP27:%.*]] = zext <16 x i8> [[TMP26]] to <16 x i16>50; CHECK-O3-NEXT: [[TMP28:%.*]] = sub nsw <16 x i16> [[TMP25]], [[TMP27]]51; CHECK-O3-NEXT: [[TMP29:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP28]], i1 false)52; CHECK-O3-NEXT: [[TMP30:%.*]] = zext <16 x i16> [[TMP29]] to <16 x i32>53; CHECK-O3-NEXT: [[TMP31:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP30]])54; CHECK-O3-NEXT: [[OP_RDX_3:%.*]] = add i32 [[TMP31]], [[OP_RDX_2]]55; CHECK-O3-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_2]], i64 [[IDX_EXT]]56; CHECK-O3-NEXT: [[ADD_PTR9_3:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_2]], i64 [[IDX_EXT8]]57; CHECK-O3-NEXT: [[TMP32:%.*]] = load <16 x i8>, ptr [[ADD_PTR_3]], align 1, !tbaa [[CHAR_TBAA0]]58; CHECK-O3-NEXT: [[TMP33:%.*]] = zext <16 x i8> [[TMP32]] to <16 x i16>59; CHECK-O3-NEXT: [[TMP34:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_3]], align 1, !tbaa [[CHAR_TBAA0]]60; CHECK-O3-NEXT: [[TMP35:%.*]] = zext <16 x i8> [[TMP34]] to <16 x i16>61; CHECK-O3-NEXT: [[TMP36:%.*]] = sub nsw <16 x i16> [[TMP33]], [[TMP35]]62; CHECK-O3-NEXT: [[TMP37:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP36]], i1 false)63; CHECK-O3-NEXT: [[TMP38:%.*]] = zext <16 x i16> [[TMP37]] to <16 x i32>64; CHECK-O3-NEXT: [[TMP39:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP38]])65; CHECK-O3-NEXT: [[OP_RDX_4:%.*]] = add i32 [[TMP39]], [[OP_RDX_3]]66; CHECK-O3-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_3]], i64 [[IDX_EXT]]67; CHECK-O3-NEXT: [[ADD_PTR9_4:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_3]], i64 [[IDX_EXT8]]68; CHECK-O3-NEXT: [[TMP40:%.*]] = load <16 x i8>, ptr [[ADD_PTR_4]], align 1, !tbaa [[CHAR_TBAA0]]69; CHECK-O3-NEXT: [[TMP41:%.*]] = zext <16 x i8> [[TMP40]] to <16 x i16>70; CHECK-O3-NEXT: [[TMP42:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_4]], align 1, !tbaa [[CHAR_TBAA0]]71; CHECK-O3-NEXT: [[TMP43:%.*]] = zext <16 x i8> [[TMP42]] to <16 x i16>72; CHECK-O3-NEXT: [[TMP44:%.*]] = sub nsw <16 x i16> [[TMP41]], [[TMP43]]73; CHECK-O3-NEXT: [[TMP45:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP44]], i1 false)74; CHECK-O3-NEXT: [[TMP46:%.*]] = zext <16 x i16> [[TMP45]] to <16 x i32>75; CHECK-O3-NEXT: [[TMP47:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP46]])76; CHECK-O3-NEXT: [[OP_RDX_5:%.*]] = add i32 [[TMP47]], [[OP_RDX_4]]77; CHECK-O3-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_4]], i64 [[IDX_EXT]]78; CHECK-O3-NEXT: [[ADD_PTR9_5:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_4]], i64 [[IDX_EXT8]]79; CHECK-O3-NEXT: [[TMP48:%.*]] = load <16 x i8>, ptr [[ADD_PTR_5]], align 1, !tbaa [[CHAR_TBAA0]]80; CHECK-O3-NEXT: [[TMP49:%.*]] = zext <16 x i8> [[TMP48]] to <16 x i16>81; CHECK-O3-NEXT: [[TMP50:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_5]], align 1, !tbaa [[CHAR_TBAA0]]82; CHECK-O3-NEXT: [[TMP51:%.*]] = zext <16 x i8> [[TMP50]] to <16 x i16>83; CHECK-O3-NEXT: [[TMP52:%.*]] = sub nsw <16 x i16> [[TMP49]], [[TMP51]]84; CHECK-O3-NEXT: [[TMP53:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP52]], i1 false)85; CHECK-O3-NEXT: [[TMP54:%.*]] = zext <16 x i16> [[TMP53]] to <16 x i32>86; CHECK-O3-NEXT: [[TMP55:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP54]])87; CHECK-O3-NEXT: [[OP_RDX_6:%.*]] = add i32 [[TMP55]], [[OP_RDX_5]]88; CHECK-O3-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_5]], i64 [[IDX_EXT]]89; CHECK-O3-NEXT: [[ADD_PTR9_6:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_5]], i64 [[IDX_EXT8]]90; CHECK-O3-NEXT: [[TMP56:%.*]] = load <16 x i8>, ptr [[ADD_PTR_6]], align 1, !tbaa [[CHAR_TBAA0]]91; CHECK-O3-NEXT: [[TMP57:%.*]] = zext <16 x i8> [[TMP56]] to <16 x i16>92; CHECK-O3-NEXT: [[TMP58:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_6]], align 1, !tbaa [[CHAR_TBAA0]]93; CHECK-O3-NEXT: [[TMP59:%.*]] = zext <16 x i8> [[TMP58]] to <16 x i16>94; CHECK-O3-NEXT: [[TMP60:%.*]] = sub nsw <16 x i16> [[TMP57]], [[TMP59]]95; CHECK-O3-NEXT: [[TMP61:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP60]], i1 false)96; CHECK-O3-NEXT: [[TMP62:%.*]] = zext <16 x i16> [[TMP61]] to <16 x i32>97; CHECK-O3-NEXT: [[TMP63:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP62]])98; CHECK-O3-NEXT: [[OP_RDX_7:%.*]] = add i32 [[TMP63]], [[OP_RDX_6]]99; CHECK-O3-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_6]], i64 [[IDX_EXT]]100; CHECK-O3-NEXT: [[ADD_PTR9_7:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_6]], i64 [[IDX_EXT8]]101; CHECK-O3-NEXT: [[TMP64:%.*]] = load <16 x i8>, ptr [[ADD_PTR_7]], align 1, !tbaa [[CHAR_TBAA0]]102; CHECK-O3-NEXT: [[TMP65:%.*]] = zext <16 x i8> [[TMP64]] to <16 x i16>103; CHECK-O3-NEXT: [[TMP66:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_7]], align 1, !tbaa [[CHAR_TBAA0]]104; CHECK-O3-NEXT: [[TMP67:%.*]] = zext <16 x i8> [[TMP66]] to <16 x i16>105; CHECK-O3-NEXT: [[TMP68:%.*]] = sub nsw <16 x i16> [[TMP65]], [[TMP67]]106; CHECK-O3-NEXT: [[TMP69:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP68]], i1 false)107; CHECK-O3-NEXT: [[TMP70:%.*]] = zext <16 x i16> [[TMP69]] to <16 x i32>108; CHECK-O3-NEXT: [[TMP71:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP70]])109; CHECK-O3-NEXT: [[OP_RDX_8:%.*]] = add i32 [[TMP71]], [[OP_RDX_7]]110; CHECK-O3-NEXT: [[ADD_PTR_8:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_7]], i64 [[IDX_EXT]]111; CHECK-O3-NEXT: [[ADD_PTR9_8:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_7]], i64 [[IDX_EXT8]]112; CHECK-O3-NEXT: [[TMP72:%.*]] = load <16 x i8>, ptr [[ADD_PTR_8]], align 1, !tbaa [[CHAR_TBAA0]]113; CHECK-O3-NEXT: [[TMP73:%.*]] = zext <16 x i8> [[TMP72]] to <16 x i16>114; CHECK-O3-NEXT: [[TMP74:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_8]], align 1, !tbaa [[CHAR_TBAA0]]115; CHECK-O3-NEXT: [[TMP75:%.*]] = zext <16 x i8> [[TMP74]] to <16 x i16>116; CHECK-O3-NEXT: [[TMP76:%.*]] = sub nsw <16 x i16> [[TMP73]], [[TMP75]]117; CHECK-O3-NEXT: [[TMP77:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP76]], i1 false)118; CHECK-O3-NEXT: [[TMP78:%.*]] = zext <16 x i16> [[TMP77]] to <16 x i32>119; CHECK-O3-NEXT: [[TMP79:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP78]])120; CHECK-O3-NEXT: [[OP_RDX_9:%.*]] = add i32 [[TMP79]], [[OP_RDX_8]]121; CHECK-O3-NEXT: [[ADD_PTR_9:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_8]], i64 [[IDX_EXT]]122; CHECK-O3-NEXT: [[ADD_PTR9_9:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_8]], i64 [[IDX_EXT8]]123; CHECK-O3-NEXT: [[TMP80:%.*]] = load <16 x i8>, ptr [[ADD_PTR_9]], align 1, !tbaa [[CHAR_TBAA0]]124; CHECK-O3-NEXT: [[TMP81:%.*]] = zext <16 x i8> [[TMP80]] to <16 x i16>125; CHECK-O3-NEXT: [[TMP82:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_9]], align 1, !tbaa [[CHAR_TBAA0]]126; CHECK-O3-NEXT: [[TMP83:%.*]] = zext <16 x i8> [[TMP82]] to <16 x i16>127; CHECK-O3-NEXT: [[TMP84:%.*]] = sub nsw <16 x i16> [[TMP81]], [[TMP83]]128; CHECK-O3-NEXT: [[TMP85:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP84]], i1 false)129; CHECK-O3-NEXT: [[TMP86:%.*]] = zext <16 x i16> [[TMP85]] to <16 x i32>130; CHECK-O3-NEXT: [[TMP87:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP86]])131; CHECK-O3-NEXT: [[OP_RDX_10:%.*]] = add i32 [[TMP87]], [[OP_RDX_9]]132; CHECK-O3-NEXT: [[ADD_PTR_10:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_9]], i64 [[IDX_EXT]]133; CHECK-O3-NEXT: [[ADD_PTR9_10:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_9]], i64 [[IDX_EXT8]]134; CHECK-O3-NEXT: [[TMP88:%.*]] = load <16 x i8>, ptr [[ADD_PTR_10]], align 1, !tbaa [[CHAR_TBAA0]]135; CHECK-O3-NEXT: [[TMP89:%.*]] = zext <16 x i8> [[TMP88]] to <16 x i16>136; CHECK-O3-NEXT: [[TMP90:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_10]], align 1, !tbaa [[CHAR_TBAA0]]137; CHECK-O3-NEXT: [[TMP91:%.*]] = zext <16 x i8> [[TMP90]] to <16 x i16>138; CHECK-O3-NEXT: [[TMP92:%.*]] = sub nsw <16 x i16> [[TMP89]], [[TMP91]]139; CHECK-O3-NEXT: [[TMP93:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP92]], i1 false)140; CHECK-O3-NEXT: [[TMP94:%.*]] = zext <16 x i16> [[TMP93]] to <16 x i32>141; CHECK-O3-NEXT: [[TMP95:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP94]])142; CHECK-O3-NEXT: [[OP_RDX_11:%.*]] = add i32 [[TMP95]], [[OP_RDX_10]]143; CHECK-O3-NEXT: [[ADD_PTR_11:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_10]], i64 [[IDX_EXT]]144; CHECK-O3-NEXT: [[ADD_PTR9_11:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_10]], i64 [[IDX_EXT8]]145; CHECK-O3-NEXT: [[TMP96:%.*]] = load <16 x i8>, ptr [[ADD_PTR_11]], align 1, !tbaa [[CHAR_TBAA0]]146; CHECK-O3-NEXT: [[TMP97:%.*]] = zext <16 x i8> [[TMP96]] to <16 x i16>147; CHECK-O3-NEXT: [[TMP98:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_11]], align 1, !tbaa [[CHAR_TBAA0]]148; CHECK-O3-NEXT: [[TMP99:%.*]] = zext <16 x i8> [[TMP98]] to <16 x i16>149; CHECK-O3-NEXT: [[TMP100:%.*]] = sub nsw <16 x i16> [[TMP97]], [[TMP99]]150; CHECK-O3-NEXT: [[TMP101:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP100]], i1 false)151; CHECK-O3-NEXT: [[TMP102:%.*]] = zext <16 x i16> [[TMP101]] to <16 x i32>152; CHECK-O3-NEXT: [[TMP103:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP102]])153; CHECK-O3-NEXT: [[OP_RDX_12:%.*]] = add i32 [[TMP103]], [[OP_RDX_11]]154; CHECK-O3-NEXT: [[ADD_PTR_12:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_11]], i64 [[IDX_EXT]]155; CHECK-O3-NEXT: [[ADD_PTR9_12:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_11]], i64 [[IDX_EXT8]]156; CHECK-O3-NEXT: [[TMP104:%.*]] = load <16 x i8>, ptr [[ADD_PTR_12]], align 1, !tbaa [[CHAR_TBAA0]]157; CHECK-O3-NEXT: [[TMP105:%.*]] = zext <16 x i8> [[TMP104]] to <16 x i16>158; CHECK-O3-NEXT: [[TMP106:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_12]], align 1, !tbaa [[CHAR_TBAA0]]159; CHECK-O3-NEXT: [[TMP107:%.*]] = zext <16 x i8> [[TMP106]] to <16 x i16>160; CHECK-O3-NEXT: [[TMP108:%.*]] = sub nsw <16 x i16> [[TMP105]], [[TMP107]]161; CHECK-O3-NEXT: [[TMP109:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP108]], i1 false)162; CHECK-O3-NEXT: [[TMP110:%.*]] = zext <16 x i16> [[TMP109]] to <16 x i32>163; CHECK-O3-NEXT: [[TMP111:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP110]])164; CHECK-O3-NEXT: [[OP_RDX_13:%.*]] = add i32 [[TMP111]], [[OP_RDX_12]]165; CHECK-O3-NEXT: [[ADD_PTR_13:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_12]], i64 [[IDX_EXT]]166; CHECK-O3-NEXT: [[ADD_PTR9_13:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_12]], i64 [[IDX_EXT8]]167; CHECK-O3-NEXT: [[TMP112:%.*]] = load <16 x i8>, ptr [[ADD_PTR_13]], align 1, !tbaa [[CHAR_TBAA0]]168; CHECK-O3-NEXT: [[TMP113:%.*]] = zext <16 x i8> [[TMP112]] to <16 x i16>169; CHECK-O3-NEXT: [[TMP114:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_13]], align 1, !tbaa [[CHAR_TBAA0]]170; CHECK-O3-NEXT: [[TMP115:%.*]] = zext <16 x i8> [[TMP114]] to <16 x i16>171; CHECK-O3-NEXT: [[TMP116:%.*]] = sub nsw <16 x i16> [[TMP113]], [[TMP115]]172; CHECK-O3-NEXT: [[TMP117:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP116]], i1 false)173; CHECK-O3-NEXT: [[TMP118:%.*]] = zext <16 x i16> [[TMP117]] to <16 x i32>174; CHECK-O3-NEXT: [[TMP119:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP118]])175; CHECK-O3-NEXT: [[OP_RDX_14:%.*]] = add i32 [[TMP119]], [[OP_RDX_13]]176; CHECK-O3-NEXT: [[ADD_PTR_14:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_13]], i64 [[IDX_EXT]]177; CHECK-O3-NEXT: [[ADD_PTR9_14:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_13]], i64 [[IDX_EXT8]]178; CHECK-O3-NEXT: [[TMP120:%.*]] = load <16 x i8>, ptr [[ADD_PTR_14]], align 1, !tbaa [[CHAR_TBAA0]]179; CHECK-O3-NEXT: [[TMP121:%.*]] = zext <16 x i8> [[TMP120]] to <16 x i16>180; CHECK-O3-NEXT: [[TMP122:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_14]], align 1, !tbaa [[CHAR_TBAA0]]181; CHECK-O3-NEXT: [[TMP123:%.*]] = zext <16 x i8> [[TMP122]] to <16 x i16>182; CHECK-O3-NEXT: [[TMP124:%.*]] = sub nsw <16 x i16> [[TMP121]], [[TMP123]]183; CHECK-O3-NEXT: [[TMP125:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP124]], i1 false)184; CHECK-O3-NEXT: [[TMP126:%.*]] = zext <16 x i16> [[TMP125]] to <16 x i32>185; CHECK-O3-NEXT: [[TMP127:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP126]])186; CHECK-O3-NEXT: [[OP_RDX_15:%.*]] = add i32 [[TMP127]], [[OP_RDX_14]]187; CHECK-O3-NEXT: ret i32 [[OP_RDX_15]]188;189; CHECK-LTO-LABEL: define dso_local i32 @test(190; CHECK-LTO-SAME: ptr noundef readonly captures(none) [[P1:%.*]], i32 noundef [[S_P1:%.*]], ptr noundef readonly captures(none) [[P2:%.*]], i32 noundef [[S_P2:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {191; CHECK-LTO-NEXT: [[ENTRY:.*:]]192; CHECK-LTO-NEXT: [[IDX_EXT8:%.*]] = sext i32 [[S_P2]] to i64193; CHECK-LTO-NEXT: [[IDX_EXT:%.*]] = sext i32 [[S_P1]] to i64194; CHECK-LTO-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[P1]], align 1, !tbaa [[CHAR_TBAA0:![0-9]+]]195; CHECK-LTO-NEXT: [[TMP1:%.*]] = zext <16 x i8> [[TMP0]] to <16 x i16>196; CHECK-LTO-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[P2]], align 1, !tbaa [[CHAR_TBAA0]]197; CHECK-LTO-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[TMP2]] to <16 x i16>198; CHECK-LTO-NEXT: [[TMP4:%.*]] = sub nsw <16 x i16> [[TMP1]], [[TMP3]]199; CHECK-LTO-NEXT: [[TMP5:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP4]], i1 true)200; CHECK-LTO-NEXT: [[TMP36:%.*]] = zext nneg <16 x i16> [[TMP5]] to <16 x i32>201; CHECK-LTO-NEXT: [[TMP44:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP36]])202; CHECK-LTO-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IDX_EXT]]203; CHECK-LTO-NEXT: [[ADD_PTR9:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IDX_EXT8]]204; CHECK-LTO-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr [[ADD_PTR]], align 1, !tbaa [[CHAR_TBAA0]]205; CHECK-LTO-NEXT: [[TMP7:%.*]] = zext <16 x i8> [[TMP6]] to <16 x i16>206; CHECK-LTO-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[ADD_PTR9]], align 1, !tbaa [[CHAR_TBAA0]]207; CHECK-LTO-NEXT: [[TMP9:%.*]] = zext <16 x i8> [[TMP8]] to <16 x i16>208; CHECK-LTO-NEXT: [[TMP10:%.*]] = sub nsw <16 x i16> [[TMP7]], [[TMP9]]209; CHECK-LTO-NEXT: [[TMP11:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP10]], i1 true)210; CHECK-LTO-NEXT: [[TMP52:%.*]] = zext nneg <16 x i16> [[TMP11]] to <16 x i32>211; CHECK-LTO-NEXT: [[TMP60:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP52]])212; CHECK-LTO-NEXT: [[OP_RDX_1:%.*]] = add i32 [[TMP60]], [[TMP44]]213; CHECK-LTO-NEXT: [[ADD_PTR_1:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]214; CHECK-LTO-NEXT: [[ADD_PTR9_1:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9]], i64 [[IDX_EXT8]]215; CHECK-LTO-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[ADD_PTR_1]], align 1, !tbaa [[CHAR_TBAA0]]216; CHECK-LTO-NEXT: [[TMP13:%.*]] = zext <16 x i8> [[TMP12]] to <16 x i16>217; CHECK-LTO-NEXT: [[TMP14:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_1]], align 1, !tbaa [[CHAR_TBAA0]]218; CHECK-LTO-NEXT: [[TMP15:%.*]] = zext <16 x i8> [[TMP14]] to <16 x i16>219; CHECK-LTO-NEXT: [[TMP16:%.*]] = sub nsw <16 x i16> [[TMP13]], [[TMP15]]220; CHECK-LTO-NEXT: [[TMP17:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP16]], i1 true)221; CHECK-LTO-NEXT: [[TMP68:%.*]] = zext nneg <16 x i16> [[TMP17]] to <16 x i32>222; CHECK-LTO-NEXT: [[TMP76:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP68]])223; CHECK-LTO-NEXT: [[OP_RDX_2:%.*]] = add i32 [[OP_RDX_1]], [[TMP76]]224; CHECK-LTO-NEXT: [[ADD_PTR_2:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_1]], i64 [[IDX_EXT]]225; CHECK-LTO-NEXT: [[ADD_PTR9_2:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_1]], i64 [[IDX_EXT8]]226; CHECK-LTO-NEXT: [[TMP18:%.*]] = load <16 x i8>, ptr [[ADD_PTR_2]], align 1, !tbaa [[CHAR_TBAA0]]227; CHECK-LTO-NEXT: [[TMP19:%.*]] = zext <16 x i8> [[TMP18]] to <16 x i16>228; CHECK-LTO-NEXT: [[TMP20:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_2]], align 1, !tbaa [[CHAR_TBAA0]]229; CHECK-LTO-NEXT: [[TMP21:%.*]] = zext <16 x i8> [[TMP20]] to <16 x i16>230; CHECK-LTO-NEXT: [[TMP22:%.*]] = sub nsw <16 x i16> [[TMP19]], [[TMP21]]231; CHECK-LTO-NEXT: [[TMP23:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP22]], i1 true)232; CHECK-LTO-NEXT: [[TMP84:%.*]] = zext nneg <16 x i16> [[TMP23]] to <16 x i32>233; CHECK-LTO-NEXT: [[TMP92:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP84]])234; CHECK-LTO-NEXT: [[OP_RDX_3:%.*]] = add i32 [[OP_RDX_2]], [[TMP92]]235; CHECK-LTO-NEXT: [[ADD_PTR_3:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_2]], i64 [[IDX_EXT]]236; CHECK-LTO-NEXT: [[ADD_PTR9_3:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_2]], i64 [[IDX_EXT8]]237; CHECK-LTO-NEXT: [[TMP24:%.*]] = load <16 x i8>, ptr [[ADD_PTR_3]], align 1, !tbaa [[CHAR_TBAA0]]238; CHECK-LTO-NEXT: [[TMP25:%.*]] = zext <16 x i8> [[TMP24]] to <16 x i16>239; CHECK-LTO-NEXT: [[TMP26:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_3]], align 1, !tbaa [[CHAR_TBAA0]]240; CHECK-LTO-NEXT: [[TMP27:%.*]] = zext <16 x i8> [[TMP26]] to <16 x i16>241; CHECK-LTO-NEXT: [[TMP28:%.*]] = sub nsw <16 x i16> [[TMP25]], [[TMP27]]242; CHECK-LTO-NEXT: [[TMP29:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP28]], i1 true)243; CHECK-LTO-NEXT: [[TMP100:%.*]] = zext nneg <16 x i16> [[TMP29]] to <16 x i32>244; CHECK-LTO-NEXT: [[TMP108:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP100]])245; CHECK-LTO-NEXT: [[OP_RDX_4:%.*]] = add i32 [[OP_RDX_3]], [[TMP108]]246; CHECK-LTO-NEXT: [[ADD_PTR_4:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_3]], i64 [[IDX_EXT]]247; CHECK-LTO-NEXT: [[ADD_PTR9_4:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_3]], i64 [[IDX_EXT8]]248; CHECK-LTO-NEXT: [[TMP30:%.*]] = load <16 x i8>, ptr [[ADD_PTR_4]], align 1, !tbaa [[CHAR_TBAA0]]249; CHECK-LTO-NEXT: [[TMP31:%.*]] = zext <16 x i8> [[TMP30]] to <16 x i16>250; CHECK-LTO-NEXT: [[TMP32:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_4]], align 1, !tbaa [[CHAR_TBAA0]]251; CHECK-LTO-NEXT: [[TMP33:%.*]] = zext <16 x i8> [[TMP32]] to <16 x i16>252; CHECK-LTO-NEXT: [[TMP34:%.*]] = sub nsw <16 x i16> [[TMP31]], [[TMP33]]253; CHECK-LTO-NEXT: [[TMP35:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP34]], i1 true)254; CHECK-LTO-NEXT: [[TMP116:%.*]] = zext nneg <16 x i16> [[TMP35]] to <16 x i32>255; CHECK-LTO-NEXT: [[TMP117:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP116]])256; CHECK-LTO-NEXT: [[OP_RDX_5:%.*]] = add i32 [[OP_RDX_4]], [[TMP117]]257; CHECK-LTO-NEXT: [[ADD_PTR_5:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_4]], i64 [[IDX_EXT]]258; CHECK-LTO-NEXT: [[ADD_PTR9_5:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_4]], i64 [[IDX_EXT8]]259; CHECK-LTO-NEXT: [[TMP37:%.*]] = load <16 x i8>, ptr [[ADD_PTR_5]], align 1, !tbaa [[CHAR_TBAA0]]260; CHECK-LTO-NEXT: [[TMP38:%.*]] = zext <16 x i8> [[TMP37]] to <16 x i16>261; CHECK-LTO-NEXT: [[TMP39:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_5]], align 1, !tbaa [[CHAR_TBAA0]]262; CHECK-LTO-NEXT: [[TMP40:%.*]] = zext <16 x i8> [[TMP39]] to <16 x i16>263; CHECK-LTO-NEXT: [[TMP41:%.*]] = sub nsw <16 x i16> [[TMP38]], [[TMP40]]264; CHECK-LTO-NEXT: [[TMP42:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP41]], i1 true)265; CHECK-LTO-NEXT: [[TMP43:%.*]] = zext nneg <16 x i16> [[TMP42]] to <16 x i32>266; CHECK-LTO-NEXT: [[TMP118:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP43]])267; CHECK-LTO-NEXT: [[OP_RDX_6:%.*]] = add i32 [[OP_RDX_5]], [[TMP118]]268; CHECK-LTO-NEXT: [[ADD_PTR_6:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_5]], i64 [[IDX_EXT]]269; CHECK-LTO-NEXT: [[ADD_PTR9_6:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_5]], i64 [[IDX_EXT8]]270; CHECK-LTO-NEXT: [[TMP45:%.*]] = load <16 x i8>, ptr [[ADD_PTR_6]], align 1, !tbaa [[CHAR_TBAA0]]271; CHECK-LTO-NEXT: [[TMP46:%.*]] = zext <16 x i8> [[TMP45]] to <16 x i16>272; CHECK-LTO-NEXT: [[TMP47:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_6]], align 1, !tbaa [[CHAR_TBAA0]]273; CHECK-LTO-NEXT: [[TMP48:%.*]] = zext <16 x i8> [[TMP47]] to <16 x i16>274; CHECK-LTO-NEXT: [[TMP49:%.*]] = sub nsw <16 x i16> [[TMP46]], [[TMP48]]275; CHECK-LTO-NEXT: [[TMP50:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP49]], i1 true)276; CHECK-LTO-NEXT: [[TMP51:%.*]] = zext nneg <16 x i16> [[TMP50]] to <16 x i32>277; CHECK-LTO-NEXT: [[TMP120:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP51]])278; CHECK-LTO-NEXT: [[OP_RDX_7:%.*]] = add i32 [[OP_RDX_6]], [[TMP120]]279; CHECK-LTO-NEXT: [[ADD_PTR_7:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_6]], i64 [[IDX_EXT]]280; CHECK-LTO-NEXT: [[ADD_PTR9_7:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_6]], i64 [[IDX_EXT8]]281; CHECK-LTO-NEXT: [[TMP53:%.*]] = load <16 x i8>, ptr [[ADD_PTR_7]], align 1, !tbaa [[CHAR_TBAA0]]282; CHECK-LTO-NEXT: [[TMP54:%.*]] = zext <16 x i8> [[TMP53]] to <16 x i16>283; CHECK-LTO-NEXT: [[TMP55:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_7]], align 1, !tbaa [[CHAR_TBAA0]]284; CHECK-LTO-NEXT: [[TMP56:%.*]] = zext <16 x i8> [[TMP55]] to <16 x i16>285; CHECK-LTO-NEXT: [[TMP57:%.*]] = sub nsw <16 x i16> [[TMP54]], [[TMP56]]286; CHECK-LTO-NEXT: [[TMP58:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP57]], i1 true)287; CHECK-LTO-NEXT: [[TMP59:%.*]] = zext nneg <16 x i16> [[TMP58]] to <16 x i32>288; CHECK-LTO-NEXT: [[TMP121:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP59]])289; CHECK-LTO-NEXT: [[OP_RDX_8:%.*]] = add i32 [[OP_RDX_7]], [[TMP121]]290; CHECK-LTO-NEXT: [[ADD_PTR_8:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_7]], i64 [[IDX_EXT]]291; CHECK-LTO-NEXT: [[ADD_PTR9_8:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_7]], i64 [[IDX_EXT8]]292; CHECK-LTO-NEXT: [[TMP61:%.*]] = load <16 x i8>, ptr [[ADD_PTR_8]], align 1, !tbaa [[CHAR_TBAA0]]293; CHECK-LTO-NEXT: [[TMP62:%.*]] = zext <16 x i8> [[TMP61]] to <16 x i16>294; CHECK-LTO-NEXT: [[TMP63:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_8]], align 1, !tbaa [[CHAR_TBAA0]]295; CHECK-LTO-NEXT: [[TMP64:%.*]] = zext <16 x i8> [[TMP63]] to <16 x i16>296; CHECK-LTO-NEXT: [[TMP65:%.*]] = sub nsw <16 x i16> [[TMP62]], [[TMP64]]297; CHECK-LTO-NEXT: [[TMP66:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP65]], i1 true)298; CHECK-LTO-NEXT: [[TMP67:%.*]] = zext nneg <16 x i16> [[TMP66]] to <16 x i32>299; CHECK-LTO-NEXT: [[TMP122:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP67]])300; CHECK-LTO-NEXT: [[OP_RDX_9:%.*]] = add i32 [[OP_RDX_8]], [[TMP122]]301; CHECK-LTO-NEXT: [[ADD_PTR_9:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_8]], i64 [[IDX_EXT]]302; CHECK-LTO-NEXT: [[ADD_PTR9_9:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_8]], i64 [[IDX_EXT8]]303; CHECK-LTO-NEXT: [[TMP69:%.*]] = load <16 x i8>, ptr [[ADD_PTR_9]], align 1, !tbaa [[CHAR_TBAA0]]304; CHECK-LTO-NEXT: [[TMP70:%.*]] = zext <16 x i8> [[TMP69]] to <16 x i16>305; CHECK-LTO-NEXT: [[TMP71:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_9]], align 1, !tbaa [[CHAR_TBAA0]]306; CHECK-LTO-NEXT: [[TMP72:%.*]] = zext <16 x i8> [[TMP71]] to <16 x i16>307; CHECK-LTO-NEXT: [[TMP73:%.*]] = sub nsw <16 x i16> [[TMP70]], [[TMP72]]308; CHECK-LTO-NEXT: [[TMP74:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP73]], i1 true)309; CHECK-LTO-NEXT: [[TMP75:%.*]] = zext nneg <16 x i16> [[TMP74]] to <16 x i32>310; CHECK-LTO-NEXT: [[TMP123:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP75]])311; CHECK-LTO-NEXT: [[OP_RDX_10:%.*]] = add i32 [[OP_RDX_9]], [[TMP123]]312; CHECK-LTO-NEXT: [[ADD_PTR_10:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_9]], i64 [[IDX_EXT]]313; CHECK-LTO-NEXT: [[ADD_PTR9_10:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_9]], i64 [[IDX_EXT8]]314; CHECK-LTO-NEXT: [[TMP77:%.*]] = load <16 x i8>, ptr [[ADD_PTR_10]], align 1, !tbaa [[CHAR_TBAA0]]315; CHECK-LTO-NEXT: [[TMP78:%.*]] = zext <16 x i8> [[TMP77]] to <16 x i16>316; CHECK-LTO-NEXT: [[TMP79:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_10]], align 1, !tbaa [[CHAR_TBAA0]]317; CHECK-LTO-NEXT: [[TMP80:%.*]] = zext <16 x i8> [[TMP79]] to <16 x i16>318; CHECK-LTO-NEXT: [[TMP81:%.*]] = sub nsw <16 x i16> [[TMP78]], [[TMP80]]319; CHECK-LTO-NEXT: [[TMP82:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP81]], i1 true)320; CHECK-LTO-NEXT: [[TMP83:%.*]] = zext nneg <16 x i16> [[TMP82]] to <16 x i32>321; CHECK-LTO-NEXT: [[TMP124:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP83]])322; CHECK-LTO-NEXT: [[OP_RDX_11:%.*]] = add i32 [[OP_RDX_10]], [[TMP124]]323; CHECK-LTO-NEXT: [[ADD_PTR_11:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_10]], i64 [[IDX_EXT]]324; CHECK-LTO-NEXT: [[ADD_PTR9_11:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_10]], i64 [[IDX_EXT8]]325; CHECK-LTO-NEXT: [[TMP85:%.*]] = load <16 x i8>, ptr [[ADD_PTR_11]], align 1, !tbaa [[CHAR_TBAA0]]326; CHECK-LTO-NEXT: [[TMP86:%.*]] = zext <16 x i8> [[TMP85]] to <16 x i16>327; CHECK-LTO-NEXT: [[TMP87:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_11]], align 1, !tbaa [[CHAR_TBAA0]]328; CHECK-LTO-NEXT: [[TMP88:%.*]] = zext <16 x i8> [[TMP87]] to <16 x i16>329; CHECK-LTO-NEXT: [[TMP89:%.*]] = sub nsw <16 x i16> [[TMP86]], [[TMP88]]330; CHECK-LTO-NEXT: [[TMP90:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP89]], i1 true)331; CHECK-LTO-NEXT: [[TMP91:%.*]] = zext nneg <16 x i16> [[TMP90]] to <16 x i32>332; CHECK-LTO-NEXT: [[TMP125:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP91]])333; CHECK-LTO-NEXT: [[OP_RDX_12:%.*]] = add i32 [[OP_RDX_11]], [[TMP125]]334; CHECK-LTO-NEXT: [[ADD_PTR_12:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_11]], i64 [[IDX_EXT]]335; CHECK-LTO-NEXT: [[ADD_PTR9_12:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_11]], i64 [[IDX_EXT8]]336; CHECK-LTO-NEXT: [[TMP93:%.*]] = load <16 x i8>, ptr [[ADD_PTR_12]], align 1, !tbaa [[CHAR_TBAA0]]337; CHECK-LTO-NEXT: [[TMP94:%.*]] = zext <16 x i8> [[TMP93]] to <16 x i16>338; CHECK-LTO-NEXT: [[TMP95:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_12]], align 1, !tbaa [[CHAR_TBAA0]]339; CHECK-LTO-NEXT: [[TMP96:%.*]] = zext <16 x i8> [[TMP95]] to <16 x i16>340; CHECK-LTO-NEXT: [[TMP97:%.*]] = sub nsw <16 x i16> [[TMP94]], [[TMP96]]341; CHECK-LTO-NEXT: [[TMP98:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP97]], i1 true)342; CHECK-LTO-NEXT: [[TMP99:%.*]] = zext nneg <16 x i16> [[TMP98]] to <16 x i32>343; CHECK-LTO-NEXT: [[TMP126:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP99]])344; CHECK-LTO-NEXT: [[OP_RDX_13:%.*]] = add i32 [[OP_RDX_12]], [[TMP126]]345; CHECK-LTO-NEXT: [[ADD_PTR_13:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_12]], i64 [[IDX_EXT]]346; CHECK-LTO-NEXT: [[ADD_PTR9_13:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_12]], i64 [[IDX_EXT8]]347; CHECK-LTO-NEXT: [[TMP101:%.*]] = load <16 x i8>, ptr [[ADD_PTR_13]], align 1, !tbaa [[CHAR_TBAA0]]348; CHECK-LTO-NEXT: [[TMP102:%.*]] = zext <16 x i8> [[TMP101]] to <16 x i16>349; CHECK-LTO-NEXT: [[TMP103:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_13]], align 1, !tbaa [[CHAR_TBAA0]]350; CHECK-LTO-NEXT: [[TMP104:%.*]] = zext <16 x i8> [[TMP103]] to <16 x i16>351; CHECK-LTO-NEXT: [[TMP105:%.*]] = sub nsw <16 x i16> [[TMP102]], [[TMP104]]352; CHECK-LTO-NEXT: [[TMP106:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP105]], i1 true)353; CHECK-LTO-NEXT: [[TMP107:%.*]] = zext nneg <16 x i16> [[TMP106]] to <16 x i32>354; CHECK-LTO-NEXT: [[TMP119:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP107]])355; CHECK-LTO-NEXT: [[OP_RDX_14:%.*]] = add i32 [[OP_RDX_13]], [[TMP119]]356; CHECK-LTO-NEXT: [[ADD_PTR_14:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR_13]], i64 [[IDX_EXT]]357; CHECK-LTO-NEXT: [[ADD_PTR9_14:%.*]] = getelementptr inbounds i8, ptr [[ADD_PTR9_13]], i64 [[IDX_EXT8]]358; CHECK-LTO-NEXT: [[TMP109:%.*]] = load <16 x i8>, ptr [[ADD_PTR_14]], align 1, !tbaa [[CHAR_TBAA0]]359; CHECK-LTO-NEXT: [[TMP110:%.*]] = zext <16 x i8> [[TMP109]] to <16 x i16>360; CHECK-LTO-NEXT: [[TMP111:%.*]] = load <16 x i8>, ptr [[ADD_PTR9_14]], align 1, !tbaa [[CHAR_TBAA0]]361; CHECK-LTO-NEXT: [[TMP112:%.*]] = zext <16 x i8> [[TMP111]] to <16 x i16>362; CHECK-LTO-NEXT: [[TMP113:%.*]] = sub nsw <16 x i16> [[TMP110]], [[TMP112]]363; CHECK-LTO-NEXT: [[TMP114:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP113]], i1 true)364; CHECK-LTO-NEXT: [[TMP115:%.*]] = zext nneg <16 x i16> [[TMP114]] to <16 x i32>365; CHECK-LTO-NEXT: [[TMP127:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP115]])366; CHECK-LTO-NEXT: [[OP_RDX_15:%.*]] = add i32 [[OP_RDX_14]], [[TMP127]]367; CHECK-LTO-NEXT: ret i32 [[OP_RDX_15]]368;369entry:370 %p1.addr = alloca ptr, align 8371 %s_p1.addr = alloca i32, align 4372 %p2.addr = alloca ptr, align 8373 %s_p2.addr = alloca i32, align 4374 %i_sum = alloca i32, align 4375 %y = alloca i32, align 4376 %cleanup.dest.slot = alloca i32, align 4377 %x = alloca i32, align 4378 store ptr %p1, ptr %p1.addr, align 8, !tbaa !4379 store i32 %s_p1, ptr %s_p1.addr, align 4, !tbaa !9380 store ptr %p2, ptr %p2.addr, align 8, !tbaa !4381 store i32 %s_p2, ptr %s_p2.addr, align 4, !tbaa !9382 call void @llvm.lifetime.start.p0(ptr %i_sum) #3383 store i32 0, ptr %i_sum, align 4, !tbaa !9384 call void @llvm.lifetime.start.p0(ptr %y) #3385 store i32 0, ptr %y, align 4, !tbaa !9386 br label %for.cond387 388for.cond: ; preds = %for.inc10, %entry389 %0 = load i32, ptr %y, align 4, !tbaa !9390 %cmp = icmp slt i32 %0, 16391 br i1 %cmp, label %for.body, label %for.cond.cleanup392 393for.cond.cleanup: ; preds = %for.cond394 store i32 2, ptr %cleanup.dest.slot, align 4395 call void @llvm.lifetime.end.p0(ptr %y) #3396 br label %for.end12397 398for.body: ; preds = %for.cond399 call void @llvm.lifetime.start.p0(ptr %x) #3400 store i32 0, ptr %x, align 4, !tbaa !9401 br label %for.cond1402 403for.cond1: ; preds = %for.inc, %for.body404 %1 = load i32, ptr %x, align 4, !tbaa !9405 %cmp2 = icmp slt i32 %1, 16406 br i1 %cmp2, label %for.body4, label %for.cond.cleanup3407 408for.cond.cleanup3: ; preds = %for.cond1409 store i32 5, ptr %cleanup.dest.slot, align 4410 call void @llvm.lifetime.end.p0(ptr %x) #3411 br label %for.end412 413for.body4: ; preds = %for.cond1414 %2 = load ptr, ptr %p1.addr, align 8, !tbaa !4415 %3 = load i32, ptr %x, align 4, !tbaa !9416 %idxprom = sext i32 %3 to i64417 %arrayidx = getelementptr inbounds i8, ptr %2, i64 %idxprom418 %4 = load i8, ptr %arrayidx, align 1, !tbaa !11419 %conv = zext i8 %4 to i32420 %5 = load ptr, ptr %p2.addr, align 8, !tbaa !4421 %6 = load i32, ptr %x, align 4, !tbaa !9422 %idxprom5 = sext i32 %6 to i64423 %arrayidx6 = getelementptr inbounds i8, ptr %5, i64 %idxprom5424 %7 = load i8, ptr %arrayidx6, align 1, !tbaa !11425 %conv7 = zext i8 %7 to i32426 %sub = sub nsw i32 %conv, %conv7427 %8 = call i32 @llvm.abs.i32(i32 %sub, i1 true)428 %9 = load i32, ptr %i_sum, align 4, !tbaa !9429 %add = add nsw i32 %9, %8430 store i32 %add, ptr %i_sum, align 4, !tbaa !9431 br label %for.inc432 433for.inc: ; preds = %for.body4434 %10 = load i32, ptr %x, align 4, !tbaa !9435 %inc = add nsw i32 %10, 1436 store i32 %inc, ptr %x, align 4, !tbaa !9437 br label %for.cond1, !llvm.loop !12438 439for.end: ; preds = %for.cond.cleanup3440 %11 = load i32, ptr %s_p1.addr, align 4, !tbaa !9441 %12 = load ptr, ptr %p1.addr, align 8, !tbaa !4442 %idx.ext = sext i32 %11 to i64443 %add.ptr = getelementptr inbounds i8, ptr %12, i64 %idx.ext444 store ptr %add.ptr, ptr %p1.addr, align 8, !tbaa !4445 %13 = load i32, ptr %s_p2.addr, align 4, !tbaa !9446 %14 = load ptr, ptr %p2.addr, align 8, !tbaa !4447 %idx.ext8 = sext i32 %13 to i64448 %add.ptr9 = getelementptr inbounds i8, ptr %14, i64 %idx.ext8449 store ptr %add.ptr9, ptr %p2.addr, align 8, !tbaa !4450 br label %for.inc10451 452for.inc10: ; preds = %for.end453 %15 = load i32, ptr %y, align 4, !tbaa !9454 %inc11 = add nsw i32 %15, 1455 store i32 %inc11, ptr %y, align 4, !tbaa !9456 br label %for.cond, !llvm.loop !14457 458for.end12: ; preds = %for.cond.cleanup459 %16 = load i32, ptr %i_sum, align 4, !tbaa !9460 store i32 1, ptr %cleanup.dest.slot, align 4461 call void @llvm.lifetime.end.p0(ptr %i_sum) #3462 ret i32 %16463}464 465; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)466declare void @llvm.lifetime.start.p0(ptr) #1467 468; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)469declare i32 @llvm.abs.i32(i32, i1 immarg) #2470 471; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)472declare void @llvm.lifetime.end.p0(ptr) #1473 474attributes #0 = { nounwind uwtable vscale_range(1,16) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+rand,+ras,+rcpc,+rdm,+sb,+spe,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a,-fmv" }475attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }476attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }477attributes #3 = { nounwind }478 479 480!4 = !{!5, !5, i64 0}481!5 = !{!"p1 omnipotent char", !6, i64 0}482!6 = !{!"any pointer", !7, i64 0}483!7 = !{!"omnipotent char", !8, i64 0}484!8 = !{!"Simple C/C++ TBAA"}485!9 = !{!10, !10, i64 0}486!10 = !{!"int", !7, i64 0}487!11 = !{!7, !7, i64 0}488!12 = distinct !{!12, !13}489!13 = !{!"llvm.loop.mustprogress"}490!14 = distinct !{!14, !13}491;.492; CHECK-O3: [[CHAR_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}493; CHECK-O3: [[META1]] = !{!"omnipotent char", [[META2:![0-9]+]], i64 0}494; CHECK-O3: [[META2]] = !{!"Simple C/C++ TBAA"}495;.496; CHECK-LTO: [[CHAR_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}497; CHECK-LTO: [[META1]] = !{!"omnipotent char", [[META2:![0-9]+]], i64 0}498; CHECK-LTO: [[META2]] = !{!"Simple C/C++ TBAA"}499;.500