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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes="default<O3>" -S | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv8.1m.main-arm-none-eabi"6 7; This should, after inlining and simplification, be a single tail predicated8; 16x vector loop handling llvm.sadd.sat. __SSAT is inlined and so is DCE'd.9 10; Function Attrs: nounwind11define dso_local void @arm_add_q7(ptr %pSrcA, ptr %pSrcB, ptr noalias %pDst, i32 %blockSize) #0 {12; CHECK-LABEL: @arm_add_q7(13; CHECK-NEXT: entry:14; CHECK-NEXT: [[CMP_NOT3:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 015; CHECK-NEXT: br i1 [[CMP_NOT3]], label [[WHILE_END:%.*]], label [[VECTOR_PH:%.*]]16; CHECK: vector.ph:17; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[BLOCKSIZE]], 1518; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -1619; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]20; CHECK: vector.body:21; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]22; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRCA:%.*]], i32 [[INDEX]]23; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i32 [[INDEX]]24; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, ptr [[PSRCB:%.*]], i32 [[INDEX]]25; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 [[BLOCKSIZE]])26; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[NEXT_GEP]], <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)27; CHECK-NEXT: [[WIDE_MASKED_LOAD16:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[NEXT_GEP15]], <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)28; CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> [[WIDE_MASKED_LOAD]], <16 x i8> [[WIDE_MASKED_LOAD16]])29; CHECK-NEXT: tail call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP2]], ptr align 1 [[NEXT_GEP14]], <16 x i1> [[ACTIVE_LANE_MASK]])30; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 1631; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]32; CHECK-NEXT: br i1 [[TMP4]], label [[WHILE_END]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]33; CHECK: while.end:34; CHECK-NEXT: ret void35;36entry:37 %pSrcA.addr = alloca ptr, align 438 %pSrcB.addr = alloca ptr, align 439 %pDst.addr = alloca ptr, align 440 %blockSize.addr = alloca i32, align 441 %blkCnt = alloca i32, align 442 store ptr %pSrcA, ptr %pSrcA.addr, align 443 store ptr %pSrcB, ptr %pSrcB.addr, align 444 store ptr %pDst, ptr %pDst.addr, align 445 store i32 %blockSize, ptr %blockSize.addr, align 446 call void @llvm.lifetime.start.p0(ptr %blkCnt)47 %0 = load i32, ptr %blockSize.addr, align 448 store i32 %0, ptr %blkCnt, align 449 br label %while.cond50 51while.cond: ; preds = %while.body, %entry52 %1 = load i32, ptr %blkCnt, align 453 %cmp = icmp ugt i32 %1, 054 br i1 %cmp, label %while.body, label %while.end55 56while.body: ; preds = %while.cond57 %2 = load ptr, ptr %pSrcA.addr, align 458 %incdec.ptr = getelementptr inbounds i8, ptr %2, i32 159 store ptr %incdec.ptr, ptr %pSrcA.addr, align 460 %3 = load i8, ptr %2, align 161 %conv = sext i8 %3 to i1662 %conv1 = sext i16 %conv to i3263 %4 = load ptr, ptr %pSrcB.addr, align 464 %incdec.ptr2 = getelementptr inbounds i8, ptr %4, i32 165 store ptr %incdec.ptr2, ptr %pSrcB.addr, align 466 %5 = load i8, ptr %4, align 167 %conv3 = sext i8 %5 to i3268 %add = add nsw i32 %conv1, %conv369 %call = call i32 @__SSAT(i32 %add, i32 8)70 %conv4 = trunc i32 %call to i871 %6 = load ptr, ptr %pDst.addr, align 472 %incdec.ptr5 = getelementptr inbounds i8, ptr %6, i32 173 store ptr %incdec.ptr5, ptr %pDst.addr, align 474 store i8 %conv4, ptr %6, align 175 %7 = load i32, ptr %blkCnt, align 476 %dec = add i32 %7, -177 store i32 %dec, ptr %blkCnt, align 478 br label %while.cond79 80while.end: ; preds = %while.cond81 call void @llvm.lifetime.end.p0(ptr %blkCnt)82 ret void83}84 85define internal i32 @__SSAT(i32 %val, i32 %sat) #1 {86entry:87 %retval = alloca i32, align 488 %val.addr = alloca i32, align 489 %sat.addr = alloca i32, align 490 %max = alloca i32, align 491 %min = alloca i32, align 492 %cleanup.dest.slot = alloca i32, align 493 store i32 %val, ptr %val.addr, align 494 store i32 %sat, ptr %sat.addr, align 495 %0 = load i32, ptr %sat.addr, align 496 %cmp = icmp uge i32 %0, 197 br i1 %cmp, label %land.lhs.true, label %if.end1098 99land.lhs.true: ; preds = %entry100 %1 = load i32, ptr %sat.addr, align 4101 %cmp1 = icmp ule i32 %1, 32102 br i1 %cmp1, label %if.then, label %if.end10103 104if.then: ; preds = %land.lhs.true105 call void @llvm.lifetime.start.p0(ptr %max)106 %2 = load i32, ptr %sat.addr, align 4107 %sub = sub i32 %2, 1108 %shl = shl i32 1, %sub109 %sub2 = sub i32 %shl, 1110 store i32 %sub2, ptr %max, align 4111 call void @llvm.lifetime.start.p0(ptr %min)112 %3 = load i32, ptr %max, align 4113 %sub3 = sub nsw i32 -1, %3114 store i32 %sub3, ptr %min, align 4115 %4 = load i32, ptr %val.addr, align 4116 %5 = load i32, ptr %max, align 4117 %cmp4 = icmp sgt i32 %4, %5118 br i1 %cmp4, label %if.then5, label %if.else119 120if.then5: ; preds = %if.then121 %6 = load i32, ptr %max, align 4122 store i32 %6, ptr %retval, align 4123 store i32 1, ptr %cleanup.dest.slot, align 4124 br label %cleanup125 126if.else: ; preds = %if.then127 %7 = load i32, ptr %val.addr, align 4128 %8 = load i32, ptr %min, align 4129 %cmp6 = icmp slt i32 %7, %8130 br i1 %cmp6, label %if.then7, label %if.end131 132if.then7: ; preds = %if.else133 %9 = load i32, ptr %min, align 4134 store i32 %9, ptr %retval, align 4135 store i32 1, ptr %cleanup.dest.slot, align 4136 br label %cleanup137 138if.end: ; preds = %if.else139 br label %if.end8140 141if.end8: ; preds = %if.end142 store i32 0, ptr %cleanup.dest.slot, align 4143 br label %cleanup144 145cleanup: ; preds = %if.end8, %if.then7, %if.then5146 call void @llvm.lifetime.end.p0(ptr %min)147 call void @llvm.lifetime.end.p0(ptr %max)148 %cleanup.dest = load i32, ptr %cleanup.dest.slot, align 4149 switch i32 %cleanup.dest, label %unreachable [150 i32 0, label %cleanup.cont151 i32 1, label %return152 ]153 154cleanup.cont: ; preds = %cleanup155 br label %if.end10156 157if.end10: ; preds = %cleanup.cont, %land.lhs.true, %entry158 %10 = load i32, ptr %val.addr, align 4159 store i32 %10, ptr %retval, align 4160 br label %return161 162return: ; preds = %if.end10, %cleanup163 %11 = load i32, ptr %retval, align 4164 ret i32 %11165 166unreachable: ; preds = %cleanup167 unreachable168}169 170declare void @llvm.lifetime.start.p0(ptr nocapture)171declare void @llvm.lifetime.end.p0(ptr nocapture)172 173attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }174attributes #1 = { alwaysinline nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }175