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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes="default<O3>" -S | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv6m-none-none-eabi"6 7; Make sure we don't make a mess of vectorization/unrolling of the remainder loop.8 9define void @arm_mean_q7(ptr noundef %pSrc, i32 noundef %blockSize, ptr noundef %pResult) #0 {10; CHECK-LABEL: @arm_mean_q7(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[BLOCKSIZE:%.*]], 413; CHECK-NEXT: [[CMP_NOT10:%.*]] = icmp eq i32 [[SHR]], 014; CHECK-NEXT: br i1 [[CMP_NOT10]], label [[WHILE_END:%.*]], label [[WHILE_BODY:%.*]]15; CHECK: while.body:16; CHECK-NEXT: [[SUM_013:%.*]] = phi i32 [ [[TMP2:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_PREHEADER:%.*]] ]17; CHECK-NEXT: [[PSRC_ADDR_012:%.*]] = phi ptr [ [[ADD_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRC:%.*]], [[WHILE_BODY_PREHEADER]] ]18; CHECK-NEXT: [[BLKCNT_011:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[SHR]], [[WHILE_BODY_PREHEADER]] ]19; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[PSRC_ADDR_012]], align 120; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> [[TMP0]], i32 0)21; CHECK-NEXT: [[TMP2]] = add i32 [[TMP1]], [[SUM_013]]22; CHECK-NEXT: [[DEC]] = add nsw i32 [[BLKCNT_011]], -123; CHECK-NEXT: [[ADD_PTR]] = getelementptr inbounds nuw i8, ptr [[PSRC_ADDR_012]], i32 1624; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 025; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT:%.*]], label [[WHILE_BODY]]26; CHECK: while.end.loopexit:27; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[BLOCKSIZE]], -1628; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[TMP3]]29; CHECK-NEXT: br label [[WHILE_END]]30; CHECK: while.end:31; CHECK-NEXT: [[PSRC_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[SCEVGEP]], [[WHILE_END_LOOPEXIT]] ]32; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[WHILE_BODY_PREHEADER]] ], [ [[TMP2]], [[WHILE_END_LOOPEXIT]] ]33; CHECK-NEXT: [[AND:%.*]] = and i32 [[BLOCKSIZE]], 1534; CHECK-NEXT: [[CMP2_NOT15:%.*]] = icmp eq i32 [[AND]], 035; CHECK-NEXT: br i1 [[CMP2_NOT15]], label [[WHILE_END5:%.*]], label [[VECTOR_BODY:%.*]]36; CHECK: vector.body:37; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 [[AND]])38; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[PSRC_ADDR_0_LCSSA]], <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)39; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i8> [[WIDE_MASKED_LOAD]] to <16 x i32>40; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i32> [[TMP4]], <16 x i32> zeroinitializer41; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP5]])42; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SUM_0_LCSSA]], [[TMP6]]43; CHECK-NEXT: br label [[WHILE_END5]]44; CHECK: while.end5:45; CHECK-NEXT: [[SUM_1_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA]], [[WHILE_END]] ], [ [[TMP7]], [[VECTOR_BODY]] ]46; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUM_1_LCSSA]], [[BLOCKSIZE]]47; CHECK-NEXT: [[CONV6:%.*]] = trunc i32 [[DIV]] to i848; CHECK-NEXT: store i8 [[CONV6]], ptr [[PRESULT:%.*]], align 149; CHECK-NEXT: ret void50;51entry:52 %pSrc.addr = alloca ptr, align 453 %blockSize.addr = alloca i32, align 454 %pResult.addr = alloca ptr, align 455 %blkCnt = alloca i32, align 456 %vecSrc = alloca <16 x i8>, align 157 %sum = alloca i32, align 458 store ptr %pSrc, ptr %pSrc.addr, align 459 store i32 %blockSize, ptr %blockSize.addr, align 460 store ptr %pResult, ptr %pResult.addr, align 461 call void @llvm.lifetime.start.p0(ptr %blkCnt) #362 call void @llvm.lifetime.start.p0(ptr %vecSrc) #363 call void @llvm.lifetime.start.p0(ptr %sum) #364 store i32 0, ptr %sum, align 465 %0 = load i32, ptr %blockSize.addr, align 466 %shr = lshr i32 %0, 467 store i32 %shr, ptr %blkCnt, align 468 br label %while.cond69 70while.cond: ; preds = %while.body, %entry71 %1 = load i32, ptr %blkCnt, align 472 %cmp = icmp ugt i32 %1, 073 br i1 %cmp, label %while.body, label %while.end74 75while.body: ; preds = %while.cond76 %2 = load ptr, ptr %pSrc.addr, align 477 %3 = load <16 x i8>, ptr %2, align 178 store <16 x i8> %3, ptr %vecSrc, align 179 %4 = load <16 x i8>, ptr %vecSrc, align 180 %5 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %4, i32 0)81 %6 = load i32, ptr %sum, align 482 %7 = add i32 %5, %683 store i32 %7, ptr %sum, align 484 %8 = load i32, ptr %blkCnt, align 485 %dec = add i32 %8, -186 store i32 %dec, ptr %blkCnt, align 487 %9 = load ptr, ptr %pSrc.addr, align 488 %add.ptr = getelementptr inbounds i8, ptr %9, i32 1689 store ptr %add.ptr, ptr %pSrc.addr, align 490 br label %while.cond91 92while.end: ; preds = %while.cond93 %10 = load i32, ptr %blockSize.addr, align 494 %and = and i32 %10, 1595 store i32 %and, ptr %blkCnt, align 496 br label %while.cond197 98while.cond1: ; preds = %while.body3, %while.end99 %11 = load i32, ptr %blkCnt, align 4100 %cmp2 = icmp ugt i32 %11, 0101 br i1 %cmp2, label %while.body3, label %while.end5102 103while.body3: ; preds = %while.cond1104 %12 = load ptr, ptr %pSrc.addr, align 4105 %incdec.ptr = getelementptr inbounds i8, ptr %12, i32 1106 store ptr %incdec.ptr, ptr %pSrc.addr, align 4107 %13 = load i8, ptr %12, align 1108 %conv = sext i8 %13 to i32109 %14 = load i32, ptr %sum, align 4110 %add = add nsw i32 %14, %conv111 store i32 %add, ptr %sum, align 4112 %15 = load i32, ptr %blkCnt, align 4113 %dec4 = add i32 %15, -1114 store i32 %dec4, ptr %blkCnt, align 4115 br label %while.cond1116 117while.end5: ; preds = %while.cond1118 %16 = load i32, ptr %sum, align 4119 %17 = load i32, ptr %blockSize.addr, align 4120 %div = sdiv i32 %16, %17121 %conv6 = trunc i32 %div to i8122 %18 = load ptr, ptr %pResult.addr, align 4123 store i8 %conv6, ptr %18, align 1124 call void @llvm.lifetime.end.p0(ptr %sum) #3125 call void @llvm.lifetime.end.p0(ptr %vecSrc) #3126 call void @llvm.lifetime.end.p0(ptr %blkCnt) #3127 ret void128}129 130declare void @llvm.lifetime.start.p0(ptr nocapture) #1131declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #2132declare void @llvm.lifetime.end.p0(ptr nocapture) #1133 134attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-pacbti,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }135attributes #1 = { argmemonly nocallback nofree nosync nounwind willreturn }136attributes #2 = { nounwind readnone }137attributes #3 = { nounwind }138