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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -O3 -S < %s | FileCheck %s3; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s4 5target triple = "x86_64--"6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"7 8; PR41813 - https://bugs.llvm.org/show_bug.cgi?id=418139 10define <4 x float> @hadd_reverse_v4f32(<4 x float> %a, <4 x float> %b) #0 {11; CHECK-LABEL: @hadd_reverse_v4f32(12; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>13; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>14; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]15; CHECK-NEXT: ret <4 x float> [[TMP3]]16;17 %shuffle = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>18 %shuffle1 = shufflevector <4 x float> %b, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>19 %vecext = extractelement <4 x float> %shuffle, i32 020 %vecext2 = extractelement <4 x float> %shuffle, i32 121 %add = fadd float %vecext, %vecext222 %vecinit = insertelement <4 x float> undef, float %add, i32 023 %vecext3 = extractelement <4 x float> %shuffle, i32 224 %vecext4 = extractelement <4 x float> %shuffle, i32 325 %add5 = fadd float %vecext3, %vecext426 %vecinit6 = insertelement <4 x float> %vecinit, float %add5, i32 127 %vecext7 = extractelement <4 x float> %shuffle1, i32 028 %vecext8 = extractelement <4 x float> %shuffle1, i32 129 %add9 = fadd float %vecext7, %vecext830 %vecinit10 = insertelement <4 x float> %vecinit6, float %add9, i32 231 %vecext11 = extractelement <4 x float> %shuffle1, i32 232 %vecext12 = extractelement <4 x float> %shuffle1, i32 333 %add13 = fadd float %vecext11, %vecext1234 %vecinit14 = insertelement <4 x float> %vecinit10, float %add13, i32 335 ret <4 x float> %vecinit1436}37 38define <4 x float> @reverse_hadd_v4f32(<4 x float> %a, <4 x float> %b) #0 {39; CHECK-LABEL: @reverse_hadd_v4f32(40; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> [[A:%.*]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>41; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[A]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>42; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]43; CHECK-NEXT: ret <4 x float> [[TMP3]]44;45 %vecext = extractelement <4 x float> %a, i32 046 %vecext1 = extractelement <4 x float> %a, i32 147 %add = fadd float %vecext, %vecext148 %vecinit = insertelement <4 x float> undef, float %add, i32 049 %vecext2 = extractelement <4 x float> %a, i32 250 %vecext3 = extractelement <4 x float> %a, i32 351 %add4 = fadd float %vecext2, %vecext352 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 153 %vecext6 = extractelement <4 x float> %b, i32 054 %vecext7 = extractelement <4 x float> %b, i32 155 %add8 = fadd float %vecext6, %vecext756 %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 257 %vecext10 = extractelement <4 x float> %b, i32 258 %vecext11 = extractelement <4 x float> %b, i32 359 %add12 = fadd float %vecext10, %vecext1160 %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 361 %shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>62 ret <4 x float> %shuffle63}64 65define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #0 {66; CHECK-LABEL: @hadd_reverse_v8f32(67; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 7, i32 5, i32 15, i32 13, i32 3, i32 1, i32 11, i32 9>68; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 6, i32 4, i32 14, i32 12, i32 2, i32 0, i32 10, i32 8>69; CHECK-NEXT: [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]70; CHECK-NEXT: ret <8 x float> [[TMP3]]71;72 %shuffle = shufflevector <8 x float> %a, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>73 %shuffle1 = shufflevector <8 x float> %b, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>74 %vecext = extractelement <8 x float> %shuffle, i32 075 %vecext2 = extractelement <8 x float> %shuffle, i32 176 %add = fadd float %vecext, %vecext277 %vecinit = insertelement <8 x float> undef, float %add, i32 078 %vecext3 = extractelement <8 x float> %shuffle, i32 279 %vecext4 = extractelement <8 x float> %shuffle, i32 380 %add5 = fadd float %vecext3, %vecext481 %vecinit6 = insertelement <8 x float> %vecinit, float %add5, i32 182 %vecext7 = extractelement <8 x float> %shuffle1, i32 083 %vecext8 = extractelement <8 x float> %shuffle1, i32 184 %add9 = fadd float %vecext7, %vecext885 %vecinit10 = insertelement <8 x float> %vecinit6, float %add9, i32 286 %vecext11 = extractelement <8 x float> %shuffle1, i32 287 %vecext12 = extractelement <8 x float> %shuffle1, i32 388 %add13 = fadd float %vecext11, %vecext1289 %vecinit14 = insertelement <8 x float> %vecinit10, float %add13, i32 390 %vecext15 = extractelement <8 x float> %shuffle, i32 491 %vecext16 = extractelement <8 x float> %shuffle, i32 592 %add17 = fadd float %vecext15, %vecext1693 %vecinit18 = insertelement <8 x float> %vecinit14, float %add17, i32 494 %vecext19 = extractelement <8 x float> %shuffle, i32 695 %vecext20 = extractelement <8 x float> %shuffle, i32 796 %add21 = fadd float %vecext19, %vecext2097 %vecinit22 = insertelement <8 x float> %vecinit18, float %add21, i32 598 %vecext23 = extractelement <8 x float> %shuffle1, i32 499 %vecext24 = extractelement <8 x float> %shuffle1, i32 5100 %add25 = fadd float %vecext23, %vecext24101 %vecinit26 = insertelement <8 x float> %vecinit22, float %add25, i32 6102 %vecext27 = extractelement <8 x float> %shuffle1, i32 6103 %vecext28 = extractelement <8 x float> %shuffle1, i32 7104 %add29 = fadd float %vecext27, %vecext28105 %vecinit30 = insertelement <8 x float> %vecinit26, float %add29, i32 7106 ret <8 x float> %vecinit30107}108 109define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {110; CHECK-LABEL: @reverse_hadd_v8f32(111; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>112; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>113; CHECK-NEXT: [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]114; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>115; CHECK-NEXT: ret <8 x float> [[SHUFFLE]]116;117 %vecext = extractelement <8 x float> %a, i32 0118 %vecext1 = extractelement <8 x float> %a, i32 1119 %add = fadd float %vecext, %vecext1120 %vecinit = insertelement <8 x float> undef, float %add, i32 0121 %vecext2 = extractelement <8 x float> %a, i32 2122 %vecext3 = extractelement <8 x float> %a, i32 3123 %add4 = fadd float %vecext2, %vecext3124 %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1125 %vecext6 = extractelement <8 x float> %b, i32 0126 %vecext7 = extractelement <8 x float> %b, i32 1127 %add8 = fadd float %vecext6, %vecext7128 %vecinit9 = insertelement <8 x float> %vecinit5, float %add8, i32 2129 %vecext10 = extractelement <8 x float> %b, i32 2130 %vecext11 = extractelement <8 x float> %b, i32 3131 %add12 = fadd float %vecext10, %vecext11132 %vecinit13 = insertelement <8 x float> %vecinit9, float %add12, i32 3133 %vecext14 = extractelement <8 x float> %a, i32 4134 %vecext15 = extractelement <8 x float> %a, i32 5135 %add16 = fadd float %vecext14, %vecext15136 %vecinit17 = insertelement <8 x float> %vecinit13, float %add16, i32 4137 %vecext18 = extractelement <8 x float> %a, i32 6138 %vecext19 = extractelement <8 x float> %a, i32 7139 %add20 = fadd float %vecext18, %vecext19140 %vecinit21 = insertelement <8 x float> %vecinit17, float %add20, i32 5141 %vecext22 = extractelement <8 x float> %b, i32 4142 %vecext23 = extractelement <8 x float> %b, i32 5143 %add24 = fadd float %vecext22, %vecext23144 %vecinit25 = insertelement <8 x float> %vecinit21, float %add24, i32 6145 %vecext26 = extractelement <8 x float> %b, i32 6146 %vecext27 = extractelement <8 x float> %b, i32 7147 %add28 = fadd float %vecext26, %vecext27148 %vecinit29 = insertelement <8 x float> %vecinit25, float %add28, i32 7149 %shuffle = shufflevector <8 x float> %vecinit29, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>150 ret <8 x float> %shuffle151}152 153attributes #0 = { "min-legal-vector-width"="128" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }154