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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -O3 -S < %s | FileCheck %s3; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s4 5target triple = "x86_64--"6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"7 8; PR42174 - https://bugs.llvm.org/show_bug.cgi?id=421749; This test should match the IR produced by clang after running -mem2reg.10; All math before the final 'add' should be scalarized.11 12define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 %h, i32 %k, i32 %w, i32 %p, i32 %j, i32 %u) {13; CHECK-LABEL: @square(14; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[K:%.*]], 215; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[P:%.*]], 623416; CHECK-NEXT: [[MUL5:%.*]] = mul nsw i32 [[H:%.*]], 7517; CHECK-NEXT: [[DIV9:%.*]] = sdiv i32 [[J:%.*]], 345218; CHECK-NEXT: [[MUL13:%.*]] = mul nsw i32 [[W:%.*]], 5319; CHECK-NEXT: [[DIV17:%.*]] = sdiv i32 [[X:%.*]], 82020; CHECK-NEXT: [[MUL21:%.*]] = shl nsw i32 [[U:%.*]], 221; CHECK-NEXT: [[OP_RDX:%.*]] = add nsw i32 [[DIV17]], 31742622; CHECK-NEXT: [[OP_RDX9:%.*]] = add nsw i32 [[DIV]], [[DIV9]]23; CHECK-NEXT: [[OP_RDX10:%.*]] = add i32 [[MUL5]], [[MUL13]]24; CHECK-NEXT: [[OP_RDX11:%.*]] = add i32 [[MUL]], [[MUL21]]25; CHECK-NEXT: [[OP_RDX12:%.*]] = add i32 [[OP_RDX]], [[OP_RDX9]]26; CHECK-NEXT: [[OP_RDX13:%.*]] = add i32 [[OP_RDX10]], [[OP_RDX11]]27; CHECK-NEXT: [[OP_RDX14:%.*]] = add i32 [[OP_RDX12]], [[OP_RDX13]]28; CHECK-NEXT: [[OP_RDX15:%.*]] = add i32 [[OP_RDX14]], [[Y:%.*]]29; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[OP_RDX15]], i64 030; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer31; CHECK-NEXT: [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]32; CHECK-NEXT: ret <4 x i32> [[ADD29]]33;34 %add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1>35 %div = sdiv i32 %k, 236 %splatinsert = insertelement <4 x i32> undef, i32 %div, i32 037 %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer38 %add1 = add <4 x i32> %add, %splat39 %mul = mul nsw i32 %p, 623440 %splatinsert2 = insertelement <4 x i32> undef, i32 %mul, i32 041 %splat3 = shufflevector <4 x i32> %splatinsert2, <4 x i32> undef, <4 x i32> zeroinitializer42 %add4 = add <4 x i32> %add1, %splat343 %mul5 = mul nsw i32 75, %h44 %splatinsert6 = insertelement <4 x i32> undef, i32 %mul5, i32 045 %splat7 = shufflevector <4 x i32> %splatinsert6, <4 x i32> undef, <4 x i32> zeroinitializer46 %add8 = add <4 x i32> %add4, %splat747 %div9 = sdiv i32 %j, 345248 %splatinsert10 = insertelement <4 x i32> undef, i32 %div9, i32 049 %splat11 = shufflevector <4 x i32> %splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer50 %add12 = add <4 x i32> %add8, %splat1151 %mul13 = mul nsw i32 53, %w52 %splatinsert14 = insertelement <4 x i32> undef, i32 %mul13, i32 053 %splat15 = shufflevector <4 x i32> %splatinsert14, <4 x i32> undef, <4 x i32> zeroinitializer54 %add16 = add <4 x i32> %add12, %splat1555 %div17 = sdiv i32 %x, 82056 %splatinsert18 = insertelement <4 x i32> undef, i32 %div17, i32 057 %splat19 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer58 %add20 = add <4 x i32> %add16, %splat1959 %mul21 = mul nsw i32 4, %u60 %splatinsert22 = insertelement <4 x i32> undef, i32 %mul21, i32 061 %splat23 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer62 %add24 = add <4 x i32> %add20, %splat2363 %splatinsert25 = insertelement <4 x i32> undef, i32 %y, i32 064 %splat26 = shufflevector <4 x i32> %splatinsert25, <4 x i32> undef, <4 x i32> zeroinitializer65 %add27 = add <4 x i32> %add24, %splat2666 %add28 = add <4 x i32> %add27, <i32 25, i32 25, i32 25, i32 25>67 %add29 = add <4 x i32> %add28, <i32 317400, i32 317400, i32 317400, i32 317400>68 ret <4 x i32> %add2969}70 71