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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s --check-prefix=SSE3; RUN: opt -passes="default<O3>" -S -mattr=avx < %s | FileCheck %s --check-prefix=AVX4 5target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"6target triple = "x86_64--"7 8%union.ElementWiseAccess = type { <4 x float> }9 10$getAt = comdat any11 12define dso_local noundef <4 x float> @ConvertVectors_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %0) #0 {13; SSE-LABEL: @ConvertVectors_ByRef(14; SSE-NEXT: [[TMP2:%.*]] = load <3 x float>, ptr [[TMP0:%.*]], align 1615; SSE-NEXT: [[TMP3:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>16; SSE-NEXT: ret <4 x float> [[TMP3]]17;18; AVX-LABEL: @ConvertVectors_ByRef(19; AVX-NEXT: [[TMP2:%.*]] = load <3 x float>, ptr [[TMP0:%.*]], align 1620; AVX-NEXT: [[TMP3:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>21; AVX-NEXT: ret <4 x float> [[TMP3]]22;23 %2 = alloca ptr, align 824 %3 = alloca <4 x float>, align 1625 store ptr %0, ptr %2, align 826 %4 = load ptr, ptr %2, align 827 %5 = call noundef nonnull align 16 dereferenceable(16) ptr @castToElementWiseAccess_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %4)28 %6 = call noundef float @getAt(ptr noundef nonnull align 16 dereferenceable(16) %5, i32 noundef 0)29 %7 = insertelement <4 x float> undef, float %6, i32 030 %8 = load ptr, ptr %2, align 831 %9 = call noundef nonnull align 16 dereferenceable(16) ptr @castToElementWiseAccess_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %8)32 %10 = call noundef float @getAt(ptr noundef nonnull align 16 dereferenceable(16) %9, i32 noundef 1)33 %11 = insertelement <4 x float> %7, float %10, i32 134 %12 = load ptr, ptr %2, align 835 %13 = call noundef nonnull align 16 dereferenceable(16) ptr @castToElementWiseAccess_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %12)36 %14 = call noundef float @getAt(ptr noundef nonnull align 16 dereferenceable(16) %13, i32 noundef 2)37 %15 = insertelement <4 x float> %11, float %14, i32 238 %16 = load ptr, ptr %2, align 839 %17 = call noundef nonnull align 16 dereferenceable(16) ptr @castToElementWiseAccess_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %16)40 %18 = call noundef float @getAt(ptr noundef nonnull align 16 dereferenceable(16) %17, i32 noundef 2)41 %19 = insertelement <4 x float> %15, float %18, i32 342 store <4 x float> %19, ptr %3, align 1643 %20 = load <4 x float>, ptr %3, align 1644 ret <4 x float> %2045}46 47define noundef <4 x float> @ConvertVectors_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %V) #0 {48; SSE-LABEL: @ConvertVectors_ByVal(49; SSE-NEXT: entry:50; SSE-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[V:%.*]], align 1651; SSE-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[V]], i64 852; SSE-NEXT: [[V_VAL421:%.*]] = load i64, ptr [[TMP1]], align 853; SSE-NEXT: [[TMP2:%.*]] = trunc i64 [[V_VAL421]] to i3254; SSE-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float55; SSE-NEXT: [[VECINIT11:%.*]] = insertelement <4 x float> [[TMP0]], float [[TMP3]], i64 256; SSE-NEXT: [[VECINIT16:%.*]] = insertelement <4 x float> [[VECINIT11]], float [[TMP3]], i64 357; SSE-NEXT: ret <4 x float> [[VECINIT16]]58;59; AVX-LABEL: @ConvertVectors_ByVal(60; AVX-NEXT: entry:61; AVX-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[V:%.*]], align 1662; AVX-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[V]], i64 863; AVX-NEXT: [[V_VAL421:%.*]] = load i64, ptr [[TMP1]], align 864; AVX-NEXT: [[TMP2:%.*]] = trunc i64 [[V_VAL421]] to i3265; AVX-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float66; AVX-NEXT: [[VECINIT11:%.*]] = insertelement <4 x float> [[TMP0]], float [[TMP3]], i64 267; AVX-NEXT: [[VECINIT16:%.*]] = insertelement <4 x float> [[VECINIT11]], float [[TMP3]], i64 368; AVX-NEXT: ret <4 x float> [[VECINIT16]]69;70entry:71 %V.addr = alloca ptr, align 872 %.compoundliteral = alloca <4 x float>, align 1673 %ref.tmp = alloca %union.ElementWiseAccess, align 1674 %ref.tmp2 = alloca %union.ElementWiseAccess, align 1675 %ref.tmp7 = alloca %union.ElementWiseAccess, align 1676 %ref.tmp12 = alloca %union.ElementWiseAccess, align 1677 store ptr %V, ptr %V.addr, align 878 call void @llvm.lifetime.start.p0(ptr %ref.tmp) #479 %0 = load ptr, ptr %V.addr, align 880 %call = call { double, double } @castToElementWiseAccess_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %0)81 %coerce.dive = getelementptr inbounds %union.ElementWiseAccess, ptr %ref.tmp, i32 0, i32 082 %1 = getelementptr inbounds { double, double }, ptr %coerce.dive, i32 0, i32 083 %2 = extractvalue { double, double } %call, 084 store double %2, ptr %1, align 1685 %3 = getelementptr inbounds { double, double }, ptr %coerce.dive, i32 0, i32 186 %4 = extractvalue { double, double } %call, 187 store double %4, ptr %3, align 888 %call1 = call noundef float @ElementWiseAccess5getAt(ptr noundef nonnull align 16 dereferenceable(16) %ref.tmp, i32 noundef 0)89 %vecinit = insertelement <4 x float> undef, float %call1, i32 090 call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #491 %5 = load ptr, ptr %V.addr, align 892 %call3 = call { double, double } @castToElementWiseAccess_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %5)93 %coerce.dive4 = getelementptr inbounds %union.ElementWiseAccess, ptr %ref.tmp2, i32 0, i32 094 %6 = getelementptr inbounds { double, double }, ptr %coerce.dive4, i32 0, i32 095 %7 = extractvalue { double, double } %call3, 096 store double %7, ptr %6, align 1697 %8 = getelementptr inbounds { double, double }, ptr %coerce.dive4, i32 0, i32 198 %9 = extractvalue { double, double } %call3, 199 store double %9, ptr %8, align 8100 %call5 = call noundef float @ElementWiseAccess5getAt(ptr noundef nonnull align 16 dereferenceable(16) %ref.tmp2, i32 noundef 1)101 %vecinit6 = insertelement <4 x float> %vecinit, float %call5, i32 1102 call void @llvm.lifetime.start.p0(ptr %ref.tmp7) #4103 %10 = load ptr, ptr %V.addr, align 8104 %call8 = call { double, double } @castToElementWiseAccess_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %10)105 %coerce.dive9 = getelementptr inbounds %union.ElementWiseAccess, ptr %ref.tmp7, i32 0, i32 0106 %11 = getelementptr inbounds { double, double }, ptr %coerce.dive9, i32 0, i32 0107 %12 = extractvalue { double, double } %call8, 0108 store double %12, ptr %11, align 16109 %13 = getelementptr inbounds { double, double }, ptr %coerce.dive9, i32 0, i32 1110 %14 = extractvalue { double, double } %call8, 1111 store double %14, ptr %13, align 8112 %call10 = call noundef float @ElementWiseAccess5getAt(ptr noundef nonnull align 16 dereferenceable(16) %ref.tmp7, i32 noundef 2)113 %vecinit11 = insertelement <4 x float> %vecinit6, float %call10, i32 2114 call void @llvm.lifetime.start.p0(ptr %ref.tmp12) #4115 %15 = load ptr, ptr %V.addr, align 8116 %call13 = call { double, double } @castToElementWiseAccess_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %15)117 %coerce.dive14 = getelementptr inbounds %union.ElementWiseAccess, ptr %ref.tmp12, i32 0, i32 0118 %16 = getelementptr inbounds { double, double }, ptr %coerce.dive14, i32 0, i32 0119 %17 = extractvalue { double, double } %call13, 0120 store double %17, ptr %16, align 16121 %18 = getelementptr inbounds { double, double }, ptr %coerce.dive14, i32 0, i32 1122 %19 = extractvalue { double, double } %call13, 1123 store double %19, ptr %18, align 8124 %call15 = call noundef float @ElementWiseAccess5getAt(ptr noundef nonnull align 16 dereferenceable(16) %ref.tmp12, i32 noundef 2)125 %vecinit16 = insertelement <4 x float> %vecinit11, float %call15, i32 3126 store <4 x float> %vecinit16, ptr %.compoundliteral, align 16127 %20 = load <4 x float>, ptr %.compoundliteral, align 16128 call void @llvm.lifetime.end.p0(ptr %ref.tmp12) #4129 call void @llvm.lifetime.end.p0(ptr %ref.tmp7) #4130 call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #4131 call void @llvm.lifetime.end.p0(ptr %ref.tmp) #4132 ret <4 x float> %20133}134 135define internal { double, double } @castToElementWiseAccess_ByVal(ptr noundef nonnull align 16 dereferenceable(16) %t) #1 {136entry:137 %retval = alloca %union.ElementWiseAccess, align 16138 %t.addr = alloca ptr, align 8139 store ptr %t, ptr %t.addr, align 8140 %0 = load ptr, ptr %t.addr, align 8141 call void @llvm.memcpy.p0.p0.i64(ptr align 16 %retval, ptr align 16 %0, i64 16, i1 false)142 %coerce.dive = getelementptr inbounds %union.ElementWiseAccess, ptr %retval, i32 0, i32 0143 %1 = load { double, double }, ptr %coerce.dive, align 16144 ret { double, double } %1145}146 147declare void @llvm.lifetime.start.p0(ptr nocapture) #2148declare void @llvm.lifetime.end.p0(ptr nocapture) #2149declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3150 151define internal noundef nonnull align 16 dereferenceable(16) ptr @castToElementWiseAccess_ByRef(ptr noundef nonnull align 16 dereferenceable(16) %0) #1 {152 %2 = alloca ptr, align 8153 store ptr %0, ptr %2, align 8154 %3 = load ptr, ptr %2, align 8155 ret ptr %3156}157 158define linkonce_odr dso_local noundef float @getAt(ptr noundef nonnull align 16 dereferenceable(16) %0, i32 noundef %1) #1 comdat align 2 {159 %3 = alloca ptr, align 8160 %4 = alloca i32, align 4161 store ptr %0, ptr %3, align 8162 store i32 %1, ptr %4, align 4163 %5 = load ptr, ptr %3, align 8164 %6 = load i32, ptr %4, align 4165 %7 = sext i32 %6 to i64166 %8 = getelementptr inbounds [4 x float], ptr %5, i64 0, i64 %7167 %9 = load float, ptr %8, align 4168 ret float %9169}170 171define linkonce_odr noundef float @ElementWiseAccess5getAt(ptr noundef nonnull align 16 dereferenceable(16) %this, i32 noundef %i) #1 align 2 {172entry:173 %this.addr = alloca ptr, align 8174 %i.addr = alloca i32, align 4175 store ptr %this, ptr %this.addr, align 8176 store i32 %i, ptr %i.addr, align 4177 %this1 = load ptr, ptr %this.addr, align 8178 %0 = load i32, ptr %i.addr, align 4179 %idxprom = sext i32 %0 to i64180 %arrayidx = getelementptr inbounds [4 x float], ptr %this1, i64 0, i64 %idxprom181 %1 = load float, ptr %arrayidx, align 4182 ret float %1183}184 185; Vector combine + SLP should form a narrow load and a vector cast186 187define void @PR51397(ptr noundef %dst, ptr noundef %srcp) {188; SSE-LABEL: @PR51397(189; SSE-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[SRCP:%.*]], align 16190; SSE-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>191; SSE-NEXT: store <4 x float> [[TMP2]], ptr [[DST:%.*]], align 16192; SSE-NEXT: ret void193;194; AVX-LABEL: @PR51397(195; AVX-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[SRCP:%.*]], align 16196; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>197; AVX-NEXT: store <4 x float> [[TMP2]], ptr [[DST:%.*]], align 16198; AVX-NEXT: ret void199;200 %src = load <8 x i32>, ptr %srcp, align 16201 %vecext = extractelement <8 x i32> %src, i32 0202 %conv = sitofp i32 %vecext to float203 %vecinit = insertelement <4 x float> undef, float %conv, i32 0204 %vecext1 = extractelement <8 x i32> %src, i32 1205 %conv2 = sitofp i32 %vecext1 to float206 %vecinit3 = insertelement <4 x float> %vecinit, float %conv2, i32 1207 %vecext4 = extractelement <8 x i32> %src, i32 2208 %conv5 = sitofp i32 %vecext4 to float209 %vecinit6 = insertelement <4 x float> %vecinit3, float %conv5, i32 2210 %vecext7 = extractelement <8 x i32> %src, i32 3211 %conv8 = sitofp i32 %vecext7 to float212 %vecinit9 = insertelement <4 x float> %vecinit6, float %conv8, i32 3213 store <4 x float> %vecinit9, ptr %dst, align 16214 ret void215}216