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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s --check-prefix=SSE3; RUN: opt -passes="default<O3>" -S -mattr=avx < %s | FileCheck %s --check-prefix=AVX4 5; This test is based on https://github.com/llvm/llvm-project/issues/507786; It's the unoptimized IR passed through -passes=mem2reg to remove obvious noise.7; This should show cooperation between instcombine, unrolling, inlining,8; and SLP to create the target-optimal vector math+logic ops.9 10target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"11target triple = "x86_64-unknown-linux-gnu"12 13define noundef i64 @foo(i64 noundef %0) {14; CHECK-LABEL: @foo(15; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 4416; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]17; CHECK-NEXT: ret i64 [[TMP3]]18;19; SSE-LABEL: @foo(20; SSE-NEXT: [[TMP2:%.*]] = xor i64 [[TMP0:%.*]], -121; SSE-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 4422; SSE-NEXT: ret i64 [[TMP3]]23;24; AVX-LABEL: @foo(25; AVX-NEXT: [[TMP2:%.*]] = xor i64 [[TMP0:%.*]], -126; AVX-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 4427; AVX-NEXT: ret i64 [[TMP3]]28;29 %2 = sub i64 1048575, %030 %3 = shl i64 %2, 4431 ret i64 %332}33 34define void @bar(ptr noundef %0) {35; SSE-LABEL: @bar(36; SSE-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[TMP0:%.*]], align 837; SSE-NEXT: [[TMP3:%.*]] = xor <2 x i64> [[TMP2]], splat (i64 -1)38; SSE-NEXT: [[TMP4:%.*]] = shl <2 x i64> [[TMP3]], splat (i64 44)39; SSE-NEXT: store <2 x i64> [[TMP4]], ptr [[TMP0]], align 840; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 1641; SSE-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP5]], align 842; SSE-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP6]], splat (i64 -1)43; SSE-NEXT: [[TMP8:%.*]] = shl <2 x i64> [[TMP7]], splat (i64 44)44; SSE-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP5]], align 845; SSE-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 3246; SSE-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 847; SSE-NEXT: [[TMP11:%.*]] = xor <2 x i64> [[TMP10]], splat (i64 -1)48; SSE-NEXT: [[TMP12:%.*]] = shl <2 x i64> [[TMP11]], splat (i64 44)49; SSE-NEXT: store <2 x i64> [[TMP12]], ptr [[TMP9]], align 850; SSE-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4851; SSE-NEXT: [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 852; SSE-NEXT: [[TMP15:%.*]] = xor <2 x i64> [[TMP14]], splat (i64 -1)53; SSE-NEXT: [[TMP16:%.*]] = shl <2 x i64> [[TMP15]], splat (i64 44)54; SSE-NEXT: store <2 x i64> [[TMP16]], ptr [[TMP13]], align 855; SSE-NEXT: ret void56;57; AVX-LABEL: @bar(58; AVX-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 859; AVX-NEXT: [[TMP3:%.*]] = xor <4 x i64> [[TMP2]], splat (i64 -1)60; AVX-NEXT: [[TMP4:%.*]] = shl <4 x i64> [[TMP3]], splat (i64 44)61; AVX-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP0]], align 862; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 3263; AVX-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 864; AVX-NEXT: [[TMP7:%.*]] = xor <4 x i64> [[TMP6]], splat (i64 -1)65; AVX-NEXT: [[TMP8:%.*]] = shl <4 x i64> [[TMP7]], splat (i64 44)66; AVX-NEXT: store <4 x i64> [[TMP8]], ptr [[TMP5]], align 867; AVX-NEXT: ret void68;69 br label %270 712: ; preds = %12, %172 %.0 = phi i32 [ 0, %1 ], [ %13, %12 ]73 %3 = icmp slt i32 %.0, 874 br i1 %3, label %5, label %475 764: ; preds = %277 br label %1478 795: ; preds = %280 %6 = sext i32 %.0 to i6481 %7 = getelementptr inbounds i64, ptr %0, i64 %682 %8 = load i64, ptr %7, align 883 %9 = call noundef i64 @foo(i64 noundef %8)84 %10 = sext i32 %.0 to i6485 %11 = getelementptr inbounds i64, ptr %0, i64 %1086 store i64 %9, ptr %11, align 887 br label %1288 8912: ; preds = %590 %13 = add nsw i32 %.0, 191 br label %292 9314: ; preds = %494 ret void95}96