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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -O2 -S -mattr=avx < %s | FileCheck %s3; RUN: opt -passes="default<O2>" -S -mattr=avx < %s | FileCheck %s4 5target triple = "x86_64--"6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"7 8define i32 @ext_ext_or_reduction_v4i32(<4 x i32> %x, <4 x i32> %y) {9; CHECK-LABEL: @ext_ext_or_reduction_v4i32(10; CHECK-NEXT: [[Z:%.*]] = and <4 x i32> [[Y:%.*]], [[X:%.*]]11; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[Z]])12; CHECK-NEXT: ret i32 [[TMP1]]13;14 %z = and <4 x i32> %x, %y15 %z0 = extractelement <4 x i32> %z, i32 016 %z1 = extractelement <4 x i32> %z, i32 117 %z01 = or i32 %z0, %z118 %z2 = extractelement <4 x i32> %z, i32 219 %z012 = or i32 %z01, %z220 %z3 = extractelement <4 x i32> %z, i32 321 %z0123 = or i32 %z3, %z01222 ret i32 %z012323}24 25define i32 @ext_ext_partial_add_reduction_v4i32(<4 x i32> %x) {26; CHECK-LABEL: @ext_ext_partial_add_reduction_v4i32(27; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>28; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]]29; CHECK-NEXT: [[SHIFT1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> <i32 2, i32 poison, i32 poison, i32 poison>30; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[SHIFT1]]31; CHECK-NEXT: [[X210:%.*]] = extractelement <4 x i32> [[TMP2]], i64 032; CHECK-NEXT: ret i32 [[X210]]33;34 %x0 = extractelement <4 x i32> %x, i32 035 %x1 = extractelement <4 x i32> %x, i32 136 %x10 = add i32 %x1, %x037 %x2 = extractelement <4 x i32> %x, i32 238 %x210 = add i32 %x2, %x1039 ret i32 %x21040}41 42define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x i32> %y) {43; CHECK-LABEL: @ext_ext_partial_add_reduction_and_extra_add_v4i32(44; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 6>45; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])46; CHECK-NEXT: ret i32 [[TMP2]]47;48 %y0 = extractelement <4 x i32> %y, i32 049 %y1 = extractelement <4 x i32> %y, i32 150 %y10 = add i32 %y1, %y051 %y2 = extractelement <4 x i32> %y, i32 252 %y210 = add i32 %y2, %y1053 %x2 = extractelement <4 x i32> %x, i32 254 %x2y210 = add i32 %x2, %y21055 ret i32 %x2y21056}57 58; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=4395359; We want to end up with a single reduction on the next 4 tests.60 61define i32 @TestVectorsEqual(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {62; CHECK-LABEL: @TestVectorsEqual(63; CHECK-NEXT: entry:64; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 465; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 466; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> [[TMP0]], [[TMP1]]67; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP2]], i1 true)68; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])69; CHECK-NEXT: [[CMP5_NOT:%.*]] = icmp sle i32 [[TMP4]], [[TOLERANCE:%.*]]70; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5_NOT]] to i3271; CHECK-NEXT: ret i32 [[COND6]]72;73entry:74 br label %for.cond75 76for.cond:77 %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]78 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]79 %cmp = icmp slt i32 %Component.0, 480 br i1 %cmp, label %for.body, label %for.cond.cleanup81 82for.cond.cleanup:83 br label %for.end84 85for.body:86 %idxprom = sext i32 %Component.0 to i6487 %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom88 %0 = load i32, ptr %arrayidx, align 489 %idxprom1 = sext i32 %Component.0 to i6490 %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom191 %1 = load i32, ptr %arrayidx2, align 492 %sub = sub nsw i32 %0, %193 %cmp3 = icmp sge i32 %sub, 094 br i1 %cmp3, label %cond.true, label %cond.false95 96cond.true:97 br label %cond.end98 99cond.false:100 %sub4 = sub nsw i32 0, %sub101 br label %cond.end102 103cond.end:104 %cond = phi i32 [ %sub, %cond.true ], [ %sub4, %cond.false ]105 %add = add nsw i32 %sum.0, %cond106 br label %for.inc107 108for.inc:109 %inc = add nsw i32 %Component.0, 1110 br label %for.cond111 112for.end:113 %cmp5 = icmp sle i32 %sum.0, %Tolerance114 %2 = zext i1 %cmp5 to i64115 %cond6 = select i1 %cmp5, i32 1, i32 0116 ret i32 %cond6117}118 119define i32 @TestVectorsEqual_alt(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {120; CHECK-LABEL: @TestVectorsEqual_alt(121; CHECK-NEXT: entry:122; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4123; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4124; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[TMP0]], [[TMP1]]125; CHECK-NEXT: [[ADD_3:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])126; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp ule i32 [[ADD_3]], [[TOLERANCE:%.*]]127; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3_NOT]] to i32128; CHECK-NEXT: ret i32 [[COND]]129;130entry:131 br label %for.cond132 133for.cond:134 %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]135 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]136 %cmp = icmp slt i32 %Component.0, 4137 br i1 %cmp, label %for.body, label %for.cond.cleanup138 139for.cond.cleanup:140 br label %for.end141 142for.body:143 %idxprom = sext i32 %Component.0 to i64144 %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom145 %0 = load i32, ptr %arrayidx, align 4146 %idxprom1 = sext i32 %Component.0 to i64147 %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1148 %1 = load i32, ptr %arrayidx2, align 4149 %sub = sub i32 %0, %1150 %add = add i32 %sum.0, %sub151 br label %for.inc152 153for.inc:154 %inc = add nsw i32 %Component.0, 1155 br label %for.cond156 157for.end:158 %cmp3 = icmp ule i32 %sum.0, %Tolerance159 %2 = zext i1 %cmp3 to i64160 %cond = select i1 %cmp3, i32 1, i32 0161 ret i32 %cond162}163 164define i32 @TestVectorsEqualFP(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {165; CHECK-LABEL: @TestVectorsEqualFP(166; CHECK-NEXT: entry:167; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4168; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4169; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]]170; CHECK-NEXT: [[TMP3:%.*]] = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])171; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP3]])172; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ole float [[TMP4]], [[TOLERANCE:%.*]]173; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32174; CHECK-NEXT: ret i32 [[COND5]]175;176entry:177 br label %for.cond178 179for.cond:180 %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]181 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]182 %cmp = icmp slt i32 %Component.0, 4183 br i1 %cmp, label %for.body, label %for.cond.cleanup184 185for.cond.cleanup:186 br label %for.end187 188for.body:189 %idxprom = sext i32 %Component.0 to i64190 %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom191 %0 = load float, ptr %arrayidx, align 4192 %idxprom1 = sext i32 %Component.0 to i64193 %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1194 %1 = load float, ptr %arrayidx2, align 4195 %sub = fsub fast float %0, %1196 %cmp3 = fcmp fast oge float %sub, 0.000000e+00197 br i1 %cmp3, label %cond.true, label %cond.false198 199cond.true:200 br label %cond.end201 202cond.false:203 %fneg = fneg fast float %sub204 br label %cond.end205 206cond.end:207 %cond = phi fast float [ %sub, %cond.true ], [ %fneg, %cond.false ]208 %add = fadd fast float %sum.0, %cond209 br label %for.inc210 211for.inc:212 %inc = add nsw i32 %Component.0, 1213 br label %for.cond214 215for.end:216 %cmp4 = fcmp fast ole float %sum.0, %Tolerance217 %2 = zext i1 %cmp4 to i64218 %cond5 = select i1 %cmp4, i32 1, i32 0219 ret i32 %cond5220}221 222define i32 @TestVectorsEqualFP_alt(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {223; CHECK-LABEL: @TestVectorsEqualFP_alt(224; CHECK-NEXT: entry:225; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4226; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4227; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]]228; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP2]])229; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP3]], [[TOLERANCE:%.*]]230; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32231; CHECK-NEXT: ret i32 [[COND]]232;233entry:234 br label %for.cond235 236for.cond:237 %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]238 %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]239 %cmp = icmp slt i32 %Component.0, 4240 br i1 %cmp, label %for.body, label %for.cond.cleanup241 242for.cond.cleanup:243 br label %for.end244 245for.body:246 %idxprom = sext i32 %Component.0 to i64247 %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom248 %0 = load float, ptr %arrayidx, align 4249 %idxprom1 = sext i32 %Component.0 to i64250 %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1251 %1 = load float, ptr %arrayidx2, align 4252 %sub = fsub fast float %0, %1253 %add = fadd fast float %sum.0, %sub254 br label %for.inc255 256for.inc:257 %inc = add nsw i32 %Component.0, 1258 br label %for.cond259 260for.end:261 %cmp3 = fcmp fast ole float %sum.0, %Tolerance262 %2 = zext i1 %cmp3 to i64263 %cond = select i1 %cmp3, i32 1, i32 0264 ret i32 %cond265}266 267; PR43745 - https://bugs.llvm.org/show_bug.cgi?id=43745268 269; FIXME: this should be vectorized270define i1 @cmp_lt_gt(double %a, double %b, double %c) {271; CHECK-LABEL: @cmp_lt_gt(272; CHECK-NEXT: entry:273; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]274; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00275; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[C:%.*]], i64 0276; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[FNEG]], i64 1277; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B]], i64 0278; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C]], i64 1279; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]]280; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[MUL]], i64 0281; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> zeroinitializer282; CHECK-NEXT: [[TMP7:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP6]]283; CHECK-NEXT: [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP7]], splat (double 0x3EB0C6F7A0B5ED8D)284; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison>285; CHECK-NEXT: [[TMP9:%.*]] = and <2 x i1> [[TMP8]], [[SHIFT]]286; CHECK-NEXT: [[OR_COND:%.*]] = extractelement <2 x i1> [[TMP9]], i64 0287; CHECK-NEXT: [[TMP10:%.*]] = fcmp ule <2 x double> [[TMP7]], splat (double 1.000000e+00)288; CHECK-NEXT: [[SHIFT2:%.*]] = shufflevector <2 x i1> [[TMP10]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison>289; CHECK-NEXT: [[TMP11:%.*]] = or <2 x i1> [[TMP10]], [[SHIFT2]]290; CHECK-NEXT: [[OR_COND1_NOT:%.*]] = extractelement <2 x i1> [[TMP11]], i64 0291; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i1 false, i1 [[OR_COND1_NOT]]292; CHECK-NEXT: ret i1 [[RETVAL_0]]293;294entry:295 %fneg = fneg double %b296 %add = fadd double %fneg, %c297 %mul = fmul double 2.0, %a298 %div = fdiv double %add, %mul299 %fneg1 = fneg double %b300 %sub = fsub double %fneg1, %c301 %mul2 = fmul double 2.0, %a302 %div3 = fdiv double %sub, %mul2303 %cmp = fcmp olt double %div, 0x3EB0C6F7A0B5ED8D304 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false305 306land.lhs.true:307 %cmp4 = fcmp olt double %div3, 0x3EB0C6F7A0B5ED8D308 br i1 %cmp4, label %if.then, label %lor.lhs.false309 310lor.lhs.false:311 %cmp5 = fcmp ogt double %div, 1.0312 br i1 %cmp5, label %land.lhs.true6, label %if.end313 314land.lhs.true6:315 %cmp7 = fcmp ogt double %div3, 1.0316 br i1 %cmp7, label %if.then, label %if.end317 318if.then:319 br label %cleanup320 321if.end:322 br label %cleanup323 324cleanup:325 %retval.0 = phi i1 [ false, %if.then ], [ true, %if.end ]326 ret i1 %retval.0327}328 329define i8 @masked_min_reduction(ptr %data, ptr %mask) {330; CHECK-LABEL: @masked_min_reduction(331; CHECK-NEXT: entry:332; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]333; CHECK: vector.body:334; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]335; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]336; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ]337; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP18:%.*]], [[VECTOR_BODY]] ]338; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ]339; CHECK-NEXT: [[DATA:%.*]] = getelementptr i8, ptr [[DATA1:%.*]], i64 [[INDEX]]340; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DATA]], i64 32341; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DATA]], i64 64342; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DATA]], i64 96343; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[DATA]], align 1344; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP1]], align 1345; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP2]], align 1346; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <32 x i8>, ptr [[TMP3]], align 1347; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[MASK:%.*]], i64 [[INDEX]]348; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP7]], i64 32349; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP7]], i64 64350; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP7]], i64 96351; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <32 x i8>, ptr [[TMP7]], align 1352; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <32 x i8>, ptr [[TMP5]], align 1353; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <32 x i8>, ptr [[TMP6]], align 1354; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <32 x i8>, ptr [[TMP22]], align 1355; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD7]], zeroinitializer356; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD8]], zeroinitializer357; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD9]], zeroinitializer358; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD10]], zeroinitializer359; CHECK-NEXT: [[TMP12:%.*]] = select <32 x i1> [[TMP8]], <32 x i8> [[WIDE_LOAD]], <32 x i8> splat (i8 -1)360; CHECK-NEXT: [[TMP13:%.*]] = select <32 x i1> [[TMP9]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> splat (i8 -1)361; CHECK-NEXT: [[TMP14:%.*]] = select <32 x i1> [[TMP10]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> splat (i8 -1)362; CHECK-NEXT: [[TMP15:%.*]] = select <32 x i1> [[TMP11]], <32 x i8> [[WIDE_LOAD6]], <32 x i8> splat (i8 -1)363; CHECK-NEXT: [[TMP16]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI]], <32 x i8> [[TMP12]])364; CHECK-NEXT: [[TMP17]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI1]], <32 x i8> [[TMP13]])365; CHECK-NEXT: [[TMP18]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI2]], <32 x i8> [[TMP14]])366; CHECK-NEXT: [[TMP19]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI3]], <32 x i8> [[TMP15]])367; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128368; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024369; CHECK-NEXT: br i1 [[TMP20]], label [[EXIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]370; CHECK: exit:371; CHECK-NEXT: [[RDX_MINMAX:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[TMP16]], <32 x i8> [[TMP17]])372; CHECK-NEXT: [[RDX_MINMAX11:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[RDX_MINMAX]], <32 x i8> [[TMP18]])373; CHECK-NEXT: [[RDX_MINMAX12:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[RDX_MINMAX11]], <32 x i8> [[TMP19]])374; CHECK-NEXT: [[TMP21:%.*]] = tail call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> [[RDX_MINMAX12]])375; CHECK-NEXT: ret i8 [[TMP21]]376;377entry:378 br label %loop379 380loop:381 %i = phi i64 [ 0, %entry ], [ %next, %loop ]382 %acc = phi i8 [ 255, %entry ], [ %acc_next, %loop ]383 384 %ptr_i = getelementptr i8, ptr %data, i64 %i385 %val = load i8, ptr %ptr_i, align 1386 387 %mask_ptr = getelementptr i8, ptr %mask, i64 %i388 %m = load i8, ptr %mask_ptr, align 1389 %cond = icmp eq i8 %m, 0390 391 ; Use select to implement masking392 %masked_val = select i1 %cond, i8 %val, i8 255393 394 ; min reduction395 %acc_next = call i8 @llvm.umin.i8(i8 %acc, i8 %masked_val)396 397 %next = add i64 %i, 1398 %cmp = icmp ult i64 %next, 1024399 br i1 %cmp, label %loop, label %exit400 401exit:402 ret i8 %acc_next403}404