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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s3 4define i64 @PR36760(i64 %a) {5; CHECK-LABEL: @PR36760(6; CHECK-NEXT: entry:7; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.smax.i64(i64 [[A:%.*]], i64 0)8; CHECK-NEXT: ret i64 [[TMP0]]9;10entry:11 %retval = alloca i64, align 812 %a.addr = alloca i64, align 813 store i64 %a, ptr %a.addr, align 814 %0 = load i64, ptr %a.addr, align 815 %cmp = icmp slt i64 %0, 016 br i1 %cmp, label %if.then, label %if.end17 18if.then:19 store i64 0, ptr %retval, align 820 br label %return21 22if.end:23 %1 = load i64, ptr %a.addr, align 824 %shr = ashr i64 %1, 6325 %2 = load i64, ptr %a.addr, align 826 %xor = xor i64 %shr, %227 store i64 %xor, ptr %retval, align 828 br label %return29 30return:31 %3 = load i64, ptr %retval, align 832 ret i64 %333}34 35define i64 @PR36760_2(i64 %a) #0 {36; CHECK-LABEL: @PR36760_2(37; CHECK-NEXT: entry:38; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.smin.i64(i64 [[A:%.*]], i64 -1)39; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], -140; CHECK-NEXT: ret i64 [[TMP1]]41;42entry:43 %retval = alloca i64, align 844 %a.addr = alloca i64, align 845 store i64 %a, ptr %a.addr, align 846 %0 = load i64, ptr %a.addr, align 847 %cmp = icmp sge i64 %0, 048 br i1 %cmp, label %if.then, label %if.end49 50if.then: ; preds = %entry51 store i64 0, ptr %retval, align 852 br label %return53 54if.end: ; preds = %entry55 %1 = load i64, ptr %a.addr, align 856 %shr = ashr i64 %1, 6357 %2 = load i64, ptr %a.addr, align 858 %xor = xor i64 %shr, %259 store i64 %xor, ptr %retval, align 860 br label %return61 62return: ; preds = %if.end, %if.then63 %3 = load i64, ptr %retval, align 864 ret i64 %365}66