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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -O2 < %s | FileCheck %s3; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s4 5; FIXME: The br -> switch conversion blocks loop rotation.6 7define i64 @test() {8; CHECK-LABEL: @test(9; CHECK-NEXT: start:10; CHECK-NEXT: br label [[BB10:%.*]]11; CHECK: bb10:12; CHECK-NEXT: [[ITER1_SROA_5_0:%.*]] = phi i64 [ 100000, [[START:%.*]] ], [ [[SPEC_SELECT:%.*]], [[BB3_I_I:%.*]] ]13; CHECK-NEXT: [[ITER1_SROA_9_0:%.*]] = phi i8 [ 2, [[START]] ], [ [[TMP3:%.*]], [[BB3_I_I]] ]14; CHECK-NEXT: [[COUNT_1:%.*]] = phi i64 [ 0, [[START]] ], [ [[TMP4:%.*]], [[BB3_I_I]] ]15; CHECK-NEXT: switch i8 [[ITER1_SROA_9_0]], label [[BB12:%.*]] [16; CHECK-NEXT: i8 2, label [[BB3_I_I]]17; CHECK-NEXT: i8 0, label [[BB3_I_I]]18; CHECK-NEXT: ]19; CHECK: bb3.i.i:20; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[ITER1_SROA_5_0]], 021; CHECK-NEXT: [[TMP3]] = zext i1 [[TMP2]] to i822; CHECK-NEXT: [[SPEC_SELECT]] = tail call i64 @llvm.usub.sat.i64(i64 [[ITER1_SROA_5_0]], i64 1)23; CHECK-NEXT: [[TMP4]] = add i64 [[COUNT_1]], [[ITER1_SROA_5_0]]24; CHECK-NEXT: br label [[BB10]]25; CHECK: bb12:26; CHECK-NEXT: ret i64 [[COUNT_1]]27;28start:29 br label %bb1030 31bb10: ; preds = %bb3.i.i, %bb632 %iter1.sroa.5.0 = phi i64 [ 100000, %start ], [ %spec.select, %bb3.i.i ]33 %iter1.sroa.9.0 = phi i8 [ 2, %start ], [ %tmp3, %bb3.i.i ]34 %count.1 = phi i64 [ 0, %start ], [ %tmp4, %bb3.i.i ]35 %c1 = icmp eq i8 %iter1.sroa.9.0, 236 %c2 = icmp eq i8 %iter1.sroa.9.0, 037 %c3 = or i1 %c1, %c238 br i1 %c3, label %bb3.i.i, label %bb1239 40bb3.i.i: ; preds = %bb10, %bb1041 %tmp2 = icmp eq i64 %iter1.sroa.5.0, 042 %tmp3 = zext i1 %tmp2 to i843 %_5.0.i.i.i.i = add i64 %iter1.sroa.5.0, -144 %spec.select = select i1 %tmp2, i64 0, i64 %_5.0.i.i.i.i45 46 %tmp4 = add i64 %count.1, %iter1.sroa.5.047 br label %bb1048 49bb12: ; preds = %bb1050 ret i64 %count.151}52