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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes='default<Os>' -S %s | FileCheck %s3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"5 6 7declare void @use(i16)8 9define void @test_remove_check_with_incrementing_integer_induction(i16 %start, i8 %len.n, i16 %a) {10; CHECK-LABEL: @test_remove_check_with_incrementing_integer_induction(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[LEN:%.*]] = zext i8 [[LEN_N:%.*]] to i1613; CHECK-NEXT: [[LEN_NEG_NOT:%.*]] = icmp ugt i16 [[A:%.*]], [[LEN]]14; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[LEN_N]], 015; CHECK-NEXT: [[OR_COND3:%.*]] = and i1 [[LEN_NEG_NOT]], [[C1]]16; CHECK-NEXT: br i1 [[OR_COND3]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]17; CHECK: loop.latch.preheader:18; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[A]], -119; CHECK-NEXT: [[TMP1:%.*]] = add nsw i16 [[LEN]], -120; CHECK-NEXT: [[UMIN:%.*]] = tail call i16 @llvm.umin.i16(i16 [[TMP0]], i16 [[TMP1]])21; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]22; CHECK: loop.latch:23; CHECK-NEXT: [[IV2:%.*]] = phi i16 [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ], [ 0, [[LOOP_LATCH_PREHEADER]] ]24; CHECK-NEXT: tail call void @use(i16 [[IV2]])25; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i16 [[IV2]], 126; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i16 [[IV2]], [[UMIN]]27; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP_LATCH]]28; CHECK: exit:29; CHECK-NEXT: ret void30;31entry:32 %len = zext i8 %len.n to i1633 %upper = add nuw nsw i16 %start, %len34 %len.neg = icmp uge i16 %len, %a35 br i1 %len.neg, label %exit, label %loop.ph36 37loop.ph:38 br label %loop.header39 40loop.header:41 %iv = phi i16 [ 0, %loop.ph ], [ %iv.next, %loop.latch ]42 %c = icmp eq i16 %iv, %len43 br i1 %c, label %exit, label %for.body44 45for.body:46 %t.1 = icmp uge i16 %iv, 047 %t.2 = icmp ult i16 %iv, %a48 %and = and i1 %t.1, %t.249 br i1 %and, label %loop.latch, label %exit50 51loop.latch:52 call void @use(i16 %iv)53 %iv.next = add nuw nsw i16 %iv, 154 br label %loop.header55 56exit:57 ret void58}59 60 61define void @chained_conditions(i64 noundef %a, i64 noundef %b, i64 noundef %c, i64 noundef %d) #0 {62; CHECK-LABEL: @chained_conditions(63; CHECK-NEXT: entry:64; CHECK-NEXT: ret void65;66entry:67 %a.addr = alloca i64, align 868 %b.addr = alloca i64, align 869 %c.addr = alloca i64, align 870 %d.addr = alloca i64, align 871 store i64 %a, ptr %a.addr, align 872 store i64 %b, ptr %b.addr, align 873 store i64 %c, ptr %c.addr, align 874 store i64 %d, ptr %d.addr, align 875 %0 = load i64, ptr %a.addr, align 876 %cmp = icmp ugt i64 %0, 204877 br i1 %cmp, label %if.then, label %lor.lhs.false78 79lor.lhs.false: ; preds = %entry80 %1 = load i64, ptr %b.addr, align 881 %cmp1 = icmp ugt i64 %1, 102482 br i1 %cmp1, label %if.then, label %lor.lhs.false283 84lor.lhs.false2: ; preds = %lor.lhs.false85 %2 = load i64, ptr %c.addr, align 886 %cmp3 = icmp ugt i64 %2, 102487 br i1 %cmp3, label %if.then, label %if.end88 89if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry90 br label %if.end1091 92if.end: ; preds = %lor.lhs.false293 %3 = load i64, ptr %a.addr, align 894 %4 = load i64, ptr %b.addr, align 895 %add = add i64 %3, %496 %5 = load i64, ptr %c.addr, align 897 %add4 = add i64 %add, %598 %6 = load i64, ptr %d.addr, align 899 %cmp5 = icmp uge i64 %add4, %6100 br i1 %cmp5, label %if.then6, label %if.end7101 102if.then6: ; preds = %if.end103 br label %if.end10104 105if.end7: ; preds = %if.end106 %7 = load i64, ptr %a.addr, align 8107 %8 = load i64, ptr %d.addr, align 8108 %cmp8 = icmp uge i64 %7, %8109 br i1 %cmp8, label %if.then9, label %if.end10110 111if.then9: ; preds = %if.end7112 call void @bar()113 br label %if.end10114 115if.end10: ; preds = %if.then, %if.then6, %if.then9, %if.end7116 ret void117}118 119declare void @bar()120