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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -O2 -S < %s | FileCheck %s3 4define <3 x float> @PR52631(<3 x float> %a, <3 x float> %b, <3 x i32> %c) {5; CHECK-LABEL: @PR52631(6; CHECK-NEXT: [[ISNEG3:%.*]] = icmp slt <3 x i32> [[C:%.*]], zeroinitializer7; CHECK-NEXT: [[OR_V:%.*]] = select <3 x i1> [[ISNEG3]], <3 x float> [[B:%.*]], <3 x float> [[A:%.*]]8; CHECK-NEXT: ret <3 x float> [[OR_V]]9;10 %a.addr = alloca <3 x float>, align 1611 %b.addr = alloca <3 x float>, align 1612 %c.addr = alloca <3 x i32>, align 1613 %zero = alloca <3 x i32>, align 1614 %mask = alloca <3 x i32>, align 1615 %res = alloca <3 x i32>, align 1616 %extractVec = shufflevector <3 x float> %a, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>17 store <4 x float> %extractVec, ptr %a.addr, align 1618 %extractVec1 = shufflevector <3 x float> %b, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>19 store <4 x float> %extractVec1, ptr %b.addr, align 1620 %extractVec3 = shufflevector <3 x i32> %c, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>21 store <4 x i32> %extractVec3, ptr %c.addr, align 1622 call void @llvm.lifetime.start.p0(ptr %zero) #223 store <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, ptr %zero, align 1624 call void @llvm.lifetime.start.p0(ptr %mask) #225 %loadVec4 = load <4 x i32>, ptr %zero, align 1626 %extractVec6 = shufflevector <4 x i32> %loadVec4, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>27 %loadVec48 = load <4 x i32>, ptr %c.addr, align 1628 %extractVec9 = shufflevector <4 x i32> %loadVec48, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>29 %cmp = icmp sgt <3 x i32> %extractVec6, %extractVec930 %sext = sext <3 x i1> %cmp to <3 x i32>31 %extractVec10 = shufflevector <3 x i32> %sext, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>32 store <4 x i32> %extractVec10, ptr %mask, align 1633 call void @llvm.lifetime.start.p0(ptr %res) #234 %loadVec413 = load <4 x i32>, ptr %mask, align 1635 %extractVec14 = shufflevector <4 x i32> %loadVec413, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>36 %loadVec416 = load <4 x float>, ptr %b.addr, align 1637 %extractVec17 = shufflevector <4 x float> %loadVec416, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>38 %astype = bitcast <3 x float> %extractVec17 to <3 x i32>39 %and = and <3 x i32> %extractVec14, %astype40 %extractVec18 = shufflevector <3 x i32> %and, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>41 store <4 x i32> %extractVec18, ptr %res, align 1642 %loadVec421 = load <4 x i32>, ptr %mask, align 1643 %extractVec22 = shufflevector <4 x i32> %loadVec421, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>44 %cmp23 = icmp eq <3 x i32> %extractVec22, zeroinitializer45 %sext24 = sext <3 x i1> %cmp23 to <3 x i32>46 %loadVec426 = load <4 x float>, ptr %a.addr, align 1647 %extractVec27 = shufflevector <4 x float> %loadVec426, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>48 %astype28 = bitcast <3 x float> %extractVec27 to <3 x i32>49 %and29 = and <3 x i32> %sext24, %astype2850 %loadVec431 = load <4 x i32>, ptr %res, align 1651 %extractVec32 = shufflevector <4 x i32> %loadVec431, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>52 %or = or <3 x i32> %and29, %extractVec3253 %astype33 = bitcast <3 x i32> %or to <3 x float>54 call void @llvm.lifetime.end.p0(ptr %res) #255 call void @llvm.lifetime.end.p0(ptr %mask) #256 call void @llvm.lifetime.end.p0(ptr %zero) #257 ret <3 x float> %astype3358}59 60define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) {61; CHECK-LABEL: @allSignBits_vec(62; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer63; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i8> [[TVAL:%.*]], <4 x i8> [[FVAL:%.*]]64; CHECK-NEXT: ret <4 x i8> [[SEL]]65;66 %bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7>67 %not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1>68 %a1 = and <4 x i8> %tval, %bitmask69 %a2 = and <4 x i8> %fval, %not_bitmask70 %sel = or <4 x i8> %a2, %a171 ret <4 x i8> %sel72}73 74define <4 x i32> @PR42100(<4 x i32> noundef %x, <4 x i32> noundef %min) {75; CHECK-LABEL: @PR42100(76; CHECK-NEXT: entry:77; CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[X:%.*]], <4 x i32> [[MIN:%.*]])78; CHECK-NEXT: ret <4 x i32> [[TMP0]]79;80entry:81 br label %for.cond82 83for.cond:84 %min.addr.0 = phi <4 x i32> [ %min, %entry ], [ %min.addr.1, %for.inc ]85 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]86 %cmp = icmp ne i32 %i.0, 487 br i1 %cmp, label %for.body, label %for.cond.cleanup88 89for.cond.cleanup:90 br label %for.end91 92for.body:93 %vecext = extractelement <4 x i32> %x, i32 %i.094 %vecext1 = extractelement <4 x i32> %min.addr.0, i32 %i.095 %cmp2 = icmp slt i32 %vecext, %vecext196 br i1 %cmp2, label %if.then, label %if.end97 98if.then:99 %vecext3 = extractelement <4 x i32> %x, i32 %i.0100 %vecins = insertelement <4 x i32> %min.addr.0, i32 %vecext3, i32 %i.0101 br label %if.end102 103if.end:104 %min.addr.1 = phi <4 x i32> [ %vecins, %if.then ], [ %min.addr.0, %for.body ]105 br label %for.inc106 107for.inc:108 %inc = add nsw i32 %i.0, 1109 br label %for.cond110 111for.end:112 ret <4 x i32> %min.addr.0113}114 115declare void @llvm.lifetime.start.p0(ptr nocapture) #1116declare void @llvm.lifetime.end.p0(ptr nocapture) #1117