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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s3target triple = "aarch64"4 5define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {6; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log(7; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {8; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()9; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 410; CHECK-NEXT: br label %[[BB3:.*]]11; CHECK: [[BB3]]:12; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]13; CHECK-NEXT: [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]14; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]15; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])16; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]17; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 118; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]19; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]20; CHECK: [[BB11]]:21; CHECK-NEXT: ret <vscale x 4 x float> [[TMP8]]22;23 %output = call <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float> %input)24 ret <vscale x 4 x float> %output25}26 27define <4 x float> @fixed_vec_log(<4 x float> %input) {28; CHECK-LABEL: define <4 x float> @fixed_vec_log(29; CHECK-SAME: <4 x float> [[INPUT:%.*]]) {30; CHECK-NEXT: [[OUTPUT:%.*]] = call <4 x float> @llvm.log.v4f32(<4 x float> [[INPUT]])31; CHECK-NEXT: ret <4 x float> [[OUTPUT]]32;33 %output = call <4 x float> @llvm.log.v4f32(<4 x float> %input)34 ret <4 x float> %output35}36 37declare <4 x float> @llvm.log.v4f32(<4 x float>) #038declare <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float>) #039 40attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }41