177 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s3 4define void @vp_fadd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {5; CHECK-LABEL: define void @vp_fadd_v4f32(6; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[RES1:%.*]] = fadd <4 x float> [[A0]], [[A1]]8; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 169; CHECK-NEXT: ret void10;11 %res = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)12 store <4 x float> %res, ptr %out13 ret void14}15declare <4 x float> @llvm.vp.fadd.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)16 17define void @vp_fsub_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {18; CHECK-LABEL: define void @vp_fsub_v4f32(19; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {20; CHECK-NEXT: [[RES1:%.*]] = fsub <4 x float> [[A0]], [[A1]]21; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1622; CHECK-NEXT: ret void23;24 %res = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)25 store <4 x float> %res, ptr %out26 ret void27}28declare <4 x float> @llvm.vp.fsub.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)29 30define void @vp_fmul_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {31; CHECK-LABEL: define void @vp_fmul_v4f32(32; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {33; CHECK-NEXT: [[RES1:%.*]] = fmul <4 x float> [[A0]], [[A1]]34; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1635; CHECK-NEXT: ret void36;37 %res = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)38 store <4 x float> %res, ptr %out39 ret void40}41declare <4 x float> @llvm.vp.fmul.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)42 43define void @vp_fdiv_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {44; CHECK-LABEL: define void @vp_fdiv_v4f32(45; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {46; CHECK-NEXT: [[RES1:%.*]] = fdiv <4 x float> [[A0]], [[A1]]47; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1648; CHECK-NEXT: ret void49;50 %res = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)51 store <4 x float> %res, ptr %out52 ret void53}54declare <4 x float> @llvm.vp.fdiv.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)55 56define void @vp_frem_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {57; CHECK-LABEL: define void @vp_frem_v4f32(58; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {59; CHECK-NEXT: [[RES1:%.*]] = frem <4 x float> [[A0]], [[A1]]60; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1661; CHECK-NEXT: ret void62;63 %res = call <4 x float> @llvm.vp.frem.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)64 store <4 x float> %res, ptr %out65 ret void66}67declare <4 x float> @llvm.vp.frem.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)68 69define void @vp_fabs_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {70; CHECK-LABEL: define void @vp_fabs_v4f32(71; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[A0]])73; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1674; CHECK-NEXT: ret void75;76 %res = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %a0, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)77 store <4 x float> %res, ptr %out78 ret void79}80declare <4 x float> @llvm.vp.fabs.v4f32(<4 x float>, <4 x i1>, i32)81 82define void @vp_sqrt_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {83; CHECK-LABEL: define void @vp_sqrt_v4f32(84; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {85; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[A0]])86; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 1687; CHECK-NEXT: ret void88;89 %res = call <4 x float> @llvm.vp.sqrt.v4f32(<4 x float> %a0, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)90 store <4 x float> %res, ptr %out91 ret void92}93declare <4 x float> @llvm.vp.sqrt.v4f32(<4 x float>, <4 x i1>, i32)94 95define void @vp_fneg_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {96; CHECK-LABEL: define void @vp_fneg_v4f32(97; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i32 [[VP:%.*]]) #[[ATTR0]] {98; CHECK-NEXT: [[RES1:%.*]] = fneg <4 x float> [[A0]]99; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 16100; CHECK-NEXT: ret void101;102 %res = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a0, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 %vp)103 store <4 x float> %res, ptr %out104 ret void105}106declare <4 x float> @llvm.vp.fneg.v4f32(<4 x float>, <4 x i1>, i32)107 108define void @vp_fma_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5) nounwind {109; CHECK-LABEL: define void @vp_fma_v4f32(110; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i4 [[A5:%.*]]) #[[ATTR0]] {111; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A1]])112; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 16113; CHECK-NEXT: ret void114;115 %res = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 4)116 store <4 x float> %res, ptr %out117 ret void118}119declare <4 x float> @llvm.vp.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, <4 x i1>, i32)120 121define void @vp_fmuladd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5) nounwind {122; CHECK-LABEL: define void @vp_fmuladd_v4f32(123; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], ptr [[OUT:%.*]], i4 [[A5:%.*]]) #[[ATTR0]] {124; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[A0]], <4 x float> [[A1]], <4 x float> [[A1]])125; CHECK-NEXT: store <4 x float> [[RES1]], ptr [[OUT]], align 16126; CHECK-NEXT: ret void127;128 %res = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a1, <4 x i1> <i1 -1, i1 -1, i1 -1, i1 -1>, i32 4)129 store <4 x float> %res, ptr %out130 ret void131}132declare <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>, <4 x i1>, i32)133 134declare <4 x float> @llvm.vp.maxnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)135define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {136; CHECK-LABEL: define <4 x float> @vfmax_vv_v4f32(137; CHECK-SAME: <4 x float> [[VA:%.*]], <4 x float> [[VB:%.*]], <4 x i1> [[M:%.*]], i32 zeroext [[EVL:%.*]]) {138; CHECK-NEXT: [[V1:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VA]], <4 x float> [[VB]])139; CHECK-NEXT: ret <4 x float> [[V1]]140;141 %v = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)142 ret <4 x float> %v143}144 145declare <8 x float> @llvm.vp.maxnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)146define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {147; CHECK-LABEL: define <8 x float> @vfmax_vv_v8f32(148; CHECK-SAME: <8 x float> [[VA:%.*]], <8 x float> [[VB:%.*]], <8 x i1> [[M:%.*]], i32 zeroext [[EVL:%.*]]) {149; CHECK-NEXT: [[V1:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[VA]], <8 x float> [[VB]])150; CHECK-NEXT: ret <8 x float> [[V1]]151;152 %v = call <8 x float> @llvm.vp.maxnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)153 ret <8 x float> %v154}155 156declare <4 x float> @llvm.vp.minnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)157define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {158; CHECK-LABEL: define <4 x float> @vfmin_vv_v4f32(159; CHECK-SAME: <4 x float> [[VA:%.*]], <4 x float> [[VB:%.*]], <4 x i1> [[M:%.*]], i32 zeroext [[EVL:%.*]]) {160; CHECK-NEXT: [[V1:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VA]], <4 x float> [[VB]])161; CHECK-NEXT: ret <4 x float> [[V1]]162;163 %v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)164 ret <4 x float> %v165}166 167declare <8 x float> @llvm.vp.minnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)168define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {169; CHECK-LABEL: define <8 x float> @vfmin_vv_v8f32(170; CHECK-SAME: <8 x float> [[VA:%.*]], <8 x float> [[VB:%.*]], <8 x i1> [[M:%.*]], i32 zeroext [[EVL:%.*]]) {171; CHECK-NEXT: [[V1:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[VA]], <8 x float> [[VB]])172; CHECK-NEXT: ret <8 x float> [[V1]]173;174 %v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)175 ret <8 x float> %v176}177