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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s3; RUN: opt -passes=pre-isel-intrinsic-lowering --expandvp-override-evl-transform=Legal --expandvp-override-mask-transform=Convert -S < %s | FileCheck %s4 5; Fixed vectors6define <2 x i64> @vpload_v2i64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {7; CHECK-LABEL: @vpload_v2i64(8; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[EVL:%.*]], i64 09; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i32> [[DOTSPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer10; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> <i32 0, i32 1>, [[DOTSPLAT]]11; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> [[TMP1]], [[M:%.*]]12; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr align 1 [[PTR:%.*]], <2 x i1> [[TMP2]], <2 x i64> poison)13; CHECK-NEXT: ret <2 x i64> [[TMP3]]14;15 %load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)16 ret <2 x i64> %load17}18 19define <2 x i64> @vpload_v2i64_vlmax(ptr %ptr, <2 x i1> %m) {20; CHECK-LABEL: @vpload_v2i64_vlmax(21; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr align 1 [[PTR:%.*]], <2 x i1> [[M:%.*]], <2 x i64> poison)22; CHECK-NEXT: ret <2 x i64> [[TMP1]]23;24 %load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> %m, i32 2)25 ret <2 x i64> %load26}27 28define <2 x i64> @vpload_v2i64_allones_mask(ptr %ptr, i32 zeroext %evl) {29; CHECK-LABEL: @vpload_v2i64_allones_mask(30; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[EVL:%.*]], i64 031; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i32> [[DOTSPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer32; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> <i32 0, i32 1>, [[DOTSPLAT]]33; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> [[TMP1]], splat (i1 true)34; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr align 1 [[PTR:%.*]], <2 x i1> [[TMP2]], <2 x i64> poison)35; CHECK-NEXT: ret <2 x i64> [[TMP3]]36;37 %load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> <i1 1, i1 1>, i32 %evl)38 ret <2 x i64> %load39}40 41define <2 x i64> @vpload_v2i64_allones_mask_vlmax(ptr %ptr) {42; CHECK-LABEL: @vpload_v2i64_allones_mask_vlmax(43; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[PTR:%.*]], align 1644; CHECK-NEXT: ret <2 x i64> [[TMP1]]45;46 %load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> <i1 1, i1 1>, i32 2)47 ret <2 x i64> %load48}49 50define void @vpstore_v2i64(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {51; CHECK-LABEL: @vpstore_v2i64(52; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[EVL:%.*]], i64 053; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i32> [[DOTSPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer54; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> <i32 0, i32 1>, [[DOTSPLAT]]55; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> [[TMP1]], [[M:%.*]]56; CHECK-NEXT: call void @llvm.masked.store.v2i64.p0(<2 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <2 x i1> [[TMP2]])57; CHECK-NEXT: ret void58;59 call void @llvm.vp.store.v2i64.p0(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 %evl)60 ret void61}62 63define void @vpstore_v2i64_vlmax(<2 x i64> %val, ptr %ptr, <2 x i1> %m) {64; CHECK-LABEL: @vpstore_v2i64_vlmax(65; CHECK-NEXT: call void @llvm.masked.store.v2i64.p0(<2 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <2 x i1> [[M:%.*]])66; CHECK-NEXT: ret void67;68 call void @llvm.vp.store.v2i64.p0(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 2)69 ret void70}71 72define void @vpstore_v2i64_allones_mask(<2 x i64> %val, ptr %ptr, i32 zeroext %evl) {73; CHECK-LABEL: @vpstore_v2i64_allones_mask(74; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[EVL:%.*]], i64 075; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i32> [[DOTSPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer76; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> <i32 0, i32 1>, [[DOTSPLAT]]77; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> [[TMP1]], splat (i1 true)78; CHECK-NEXT: call void @llvm.masked.store.v2i64.p0(<2 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <2 x i1> [[TMP2]])79; CHECK-NEXT: ret void80;81 call void @llvm.vp.store.v2i64.p0(<2 x i64> %val, ptr %ptr, <2 x i1> <i1 1, i1 1>, i32 %evl)82 ret void83}84 85define void @vpstore_v2i64_allones_mask_vlmax(<2 x i64> %val, ptr %ptr) {86; CHECK-LABEL: @vpstore_v2i64_allones_mask_vlmax(87; CHECK-NEXT: store <2 x i64> [[VAL:%.*]], ptr [[PTR:%.*]], align 1688; CHECK-NEXT: ret void89;90 call void @llvm.vp.store.v2i64.p0(<2 x i64> %val, ptr %ptr, <2 x i1> <i1 1, i1 1>, i32 2)91 ret void92}93 94; Scalable vectors95define <vscale x 1 x i64> @vpload_nxv1i64(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {96; CHECK-LABEL: @vpload_nxv1i64(97; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])98; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], [[M:%.*]]99; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()100; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1101; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 1 x i64> @llvm.masked.load.nxv1i64.p0(ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[TMP2]], <vscale x 1 x i64> poison)102; CHECK-NEXT: ret <vscale x 1 x i64> [[TMP3]]103;104 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)105 ret <vscale x 1 x i64> %load106}107 108define <vscale x 1 x i64> @vpload_nxv1i64_vscale(ptr %ptr, <vscale x 1 x i1> %m) {109; CHECK-LABEL: @vpload_nxv1i64_vscale(110; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()111; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1112; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.masked.load.nxv1i64.p0(ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[M:%.*]], <vscale x 1 x i64> poison)113; CHECK-NEXT: ret <vscale x 1 x i64> [[TMP1]]114;115 %vscale = call i32 @llvm.vscale.i32()116 %vlmax = mul nuw i32 %vscale, 1117 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %vlmax)118 ret <vscale x 1 x i64> %load119}120 121define <vscale x 1 x i64> @vpload_nxv1i64_allones_mask(ptr %ptr, i32 zeroext %evl) {122; CHECK-LABEL: @vpload_nxv1i64_allones_mask(123; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])124; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], splat (i1 true)125; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()126; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1127; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 1 x i64> @llvm.masked.load.nxv1i64.p0(ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[TMP2]], <vscale x 1 x i64> poison)128; CHECK-NEXT: ret <vscale x 1 x i64> [[TMP3]]129;130 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)131 ret <vscale x 1 x i64> %load132}133 134define <vscale x 1 x i64> @vpload_nxv1i64_allones_mask_vscale(ptr %ptr) {135; CHECK-LABEL: @vpload_nxv1i64_allones_mask_vscale(136; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()137; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1138; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 1 x i64>, ptr [[PTR:%.*]], align 8139; CHECK-NEXT: ret <vscale x 1 x i64> [[TMP1]]140;141 %vscale = call i32 @llvm.vscale.i32()142 %vlmax = mul nuw i32 %vscale, 1143 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %vlmax)144 ret <vscale x 1 x i64> %load145}146 147define void @vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {148; CHECK-LABEL: @vpstore_nxv1i64(149; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])150; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], [[M:%.*]]151; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()152; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1153; CHECK-NEXT: call void @llvm.masked.store.nxv1i64.p0(<vscale x 1 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[TMP2]])154; CHECK-NEXT: ret void155;156 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)157 ret void158}159 160define void @vpstore_nxv1i64_vscale(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {161; CHECK-LABEL: @vpstore_nxv1i64_vscale(162; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()163; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1164; CHECK-NEXT: call void @llvm.masked.store.nxv1i64.p0(<vscale x 1 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[M:%.*]])165; CHECK-NEXT: ret void166;167 %vscale = call i32 @llvm.vscale.i32()168 %vlmax = mul nuw i32 %vscale, 1169 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %vlmax)170 ret void171}172 173define void @vpstore_nxv1i64_allones_mask(<vscale x 1 x i64> %val, ptr %ptr, i32 zeroext %evl) {174; CHECK-LABEL: @vpstore_nxv1i64_allones_mask(175; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])176; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], splat (i1 true)177; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()178; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1179; CHECK-NEXT: call void @llvm.masked.store.nxv1i64.p0(<vscale x 1 x i64> [[VAL:%.*]], ptr align 1 [[PTR:%.*]], <vscale x 1 x i1> [[TMP2]])180; CHECK-NEXT: ret void181;182 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)183 ret void184}185 186define void @vpstore_nxv1i64_allones_mask_vscale(<vscale x 1 x i64> %val, ptr %ptr) {187; CHECK-LABEL: @vpstore_nxv1i64_allones_mask_vscale(188; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()189; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1190; CHECK-NEXT: store <vscale x 1 x i64> [[VAL:%.*]], ptr [[PTR:%.*]], align 8191; CHECK-NEXT: ret void192;193 %vscale = call i32 @llvm.vscale.i32()194 %vlmax = mul nuw i32 %vscale, 1195 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %vlmax)196 ret void197}198 199declare i32 @llvm.vscale.i32()200 201declare <2 x i64> @llvm.vp.load.v2i64.p0(ptr, <2 x i1>, i32)202declare void @llvm.vp.store.v2i64.p0(<2 x i64>, ptr, <2 x i1>, i32)203 204declare <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr, <vscale x 1 x i1>, i32)205declare void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64>, ptr, <vscale x 1 x i1>, i32)206