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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=sccp -S < %s | FileCheck %s3 4 5; PR69406define double @test1() {7; CHECK-LABEL: @test1(8; CHECK-NEXT: [[T:%.*]] = sitofp i32 undef to double9; CHECK-NEXT: ret double [[T]]10;11 %t = sitofp i32 undef to double12 ret double %t13}14 15 16; rdar://783237017; Check that lots of stuff doesn't get turned into undef.18define i32 @test2() nounwind readnone ssp {19; CHECK-LABEL: @test2(20; CHECK-NEXT: init:21; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER:%.*]]22; CHECK: control.outer.loopexit.us-lcssa:23; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT:%.*]]24; CHECK: control.outer.loopexit:25; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE:%.*]]26; CHECK: control.outer.outer:27; CHECK-NEXT: [[SWITCHCOND_0_PH_PH:%.*]] = phi i32 [ 2, [[INIT:%.*]] ], [ 3, [[CONTROL_OUTER_OUTER_BACKEDGE]] ]28; CHECK-NEXT: [[I_0_PH_PH:%.*]] = phi i32 [ undef, [[INIT]] ], [ [[I_0_PH_PH_BE:%.*]], [[CONTROL_OUTER_OUTER_BACKEDGE]] ]29; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[I_0_PH_PH]], 030; CHECK-NEXT: br i1 [[TMP4]], label [[CONTROL_OUTER_OUTER_SPLIT_US:%.*]], label [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE:%.*]]31; CHECK: control.outer.outer.control.outer.outer.split_crit_edge:32; CHECK-NEXT: br label [[CONTROL_OUTER:%.*]]33; CHECK: control.outer.outer.split.us:34; CHECK-NEXT: br label [[CONTROL_OUTER_US:%.*]]35; CHECK: control.outer.us:36; CHECK-NEXT: [[A_0_PH_US:%.*]] = phi i32 [ 3, [[BB3_US:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_SPLIT_US]] ]37; CHECK-NEXT: [[SWITCHCOND_0_PH_US:%.*]] = phi i32 [ [[A_0_PH_US]], [[BB3_US]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_SPLIT_US]] ]38; CHECK-NEXT: br label [[CONTROL_US:%.*]]39; CHECK: bb3.us:40; CHECK-NEXT: br label [[CONTROL_OUTER_US]]41; CHECK: bb0.us:42; CHECK-NEXT: br label [[CONTROL_US]]43; CHECK: control.us:44; CHECK-NEXT: [[SWITCHCOND_0_US:%.*]] = phi i32 [ [[A_0_PH_US]], [[BB0_US:%.*]] ], [ [[SWITCHCOND_0_PH_US]], [[CONTROL_OUTER_US]] ]45; CHECK-NEXT: switch i32 [[SWITCHCOND_0_US]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA_US:%.*]] [46; CHECK-NEXT: i32 0, label [[BB0_US]]47; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA_US:%.*]]48; CHECK-NEXT: i32 3, label [[BB3_US]]49; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA_US:%.*]]50; CHECK-NEXT: ]51; CHECK: control.outer.loopexit.us-lcssa.us:52; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT]]53; CHECK: bb1.us-lcssa.us:54; CHECK-NEXT: br label [[BB1:%.*]]55; CHECK: bb4.us-lcssa.us:56; CHECK-NEXT: br label [[BB4:%.*]]57; CHECK: control.outer:58; CHECK-NEXT: [[A_0_PH:%.*]] = phi i32 [ 1, [[BB3:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ]59; CHECK-NEXT: [[SWITCHCOND_0_PH:%.*]] = phi i32 [ 0, [[BB3]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ]60; CHECK-NEXT: br label [[CONTROL:%.*]]61; CHECK: control:62; CHECK-NEXT: [[SWITCHCOND_0:%.*]] = phi i32 [ [[A_0_PH]], [[BB0:%.*]] ], [ [[SWITCHCOND_0_PH]], [[CONTROL_OUTER]] ]63; CHECK-NEXT: switch i32 [[SWITCHCOND_0]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA:%.*]] [64; CHECK-NEXT: i32 0, label [[BB0]]65; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA:%.*]]66; CHECK-NEXT: i32 3, label [[BB3]]67; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA:%.*]]68; CHECK-NEXT: ]69; CHECK: bb4.us-lcssa:70; CHECK-NEXT: br label [[BB4]]71; CHECK: bb4:72; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE]]73; CHECK: control.outer.outer.backedge:74; CHECK-NEXT: [[I_0_PH_PH_BE]] = phi i32 [ 1, [[BB4]] ], [ 0, [[CONTROL_OUTER_LOOPEXIT]] ]75; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER]]76; CHECK: bb3:77; CHECK-NEXT: br label [[CONTROL_OUTER]]78; CHECK: bb0:79; CHECK-NEXT: br label [[CONTROL]]80; CHECK: bb1.us-lcssa:81; CHECK-NEXT: br label [[BB1]]82; CHECK: bb1:83; CHECK-NEXT: ret i32 084;85init:86 br label %control.outer.outer87 88control.outer.loopexit.us-lcssa: ; preds = %control89 br label %control.outer.loopexit90 91control.outer.loopexit: ; preds = %control.outer.loopexit.us-lcssa.us, %control.outer.loopexit.us-lcssa92 br label %control.outer.outer.backedge93 94control.outer.outer: ; preds = %control.outer.outer.backedge, %init95 %switchCond.0.ph.ph = phi i32 [ 2, %init ], [ 3, %control.outer.outer.backedge ] ; <i32> [#uses=2]96 %i.0.ph.ph = phi i32 [ undef, %init ], [ %i.0.ph.ph.be, %control.outer.outer.backedge ] ; <i32> [#uses=1]97 %tmp4 = icmp eq i32 %i.0.ph.ph, 0 ; <i1> [#uses=1]98 br i1 %tmp4, label %control.outer.outer.split.us, label %control.outer.outer.control.outer.outer.split_crit_edge99 100control.outer.outer.control.outer.outer.split_crit_edge: ; preds = %control.outer.outer101 br label %control.outer102 103control.outer.outer.split.us: ; preds = %control.outer.outer104 br label %control.outer.us105 106control.outer.us: ; preds = %bb3.us, %control.outer.outer.split.us107 %A.0.ph.us = phi i32 [ %switchCond.0.us, %bb3.us ], [ 4, %control.outer.outer.split.us ] ; <i32> [#uses=2]108 %switchCond.0.ph.us = phi i32 [ %A.0.ph.us, %bb3.us ], [ %switchCond.0.ph.ph, %control.outer.outer.split.us ] ; <i32> [#uses=1]109 br label %control.us110 111bb3.us: ; preds = %control.us112 br label %control.outer.us113 114bb0.us: ; preds = %control.us115 br label %control.us116 117control.us: ; preds = %bb0.us, %control.outer.us118 %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; <i32> [#uses=2]119 switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [120 i32 0, label %bb0.us121 i32 1, label %bb1.us-lcssa.us122 i32 3, label %bb3.us123 i32 4, label %bb4.us-lcssa.us124 ]125 126control.outer.loopexit.us-lcssa.us: ; preds = %control.us127 br label %control.outer.loopexit128 129bb1.us-lcssa.us: ; preds = %control.us130 br label %bb1131 132bb4.us-lcssa.us: ; preds = %control.us133 br label %bb4134 135control.outer: ; preds = %bb3, %control.outer.outer.control.outer.outer.split_crit_edge136 %A.0.ph = phi i32 [ %nextId17, %bb3 ], [ 4, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1]137 %switchCond.0.ph = phi i32 [ 0, %bb3 ], [ %switchCond.0.ph.ph, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1]138 br label %control139 140control: ; preds = %bb0, %control.outer141 %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; <i32> [#uses=2]142 switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [143 i32 0, label %bb0144 i32 1, label %bb1.us-lcssa145 i32 3, label %bb3146 i32 4, label %bb4.us-lcssa147 ]148 149bb4.us-lcssa: ; preds = %control150 br label %bb4151 152bb4: ; preds = %bb4.us-lcssa, %bb4.us-lcssa.us153 br label %control.outer.outer.backedge154 155control.outer.outer.backedge: ; preds = %bb4, %control.outer.loopexit156 %i.0.ph.ph.be = phi i32 [ 1, %bb4 ], [ 0, %control.outer.loopexit ] ; <i32> [#uses=1]157 br label %control.outer.outer158 159bb3: ; preds = %control160 %nextId17 = add i32 %switchCond.0, -2 ; <i32> [#uses=1]161 br label %control.outer162 163bb0: ; preds = %control164 br label %control165 166bb1.us-lcssa: ; preds = %control167 br label %bb1168 169bb1: ; preds = %bb1.us-lcssa, %bb1.us-lcssa.us170 ret i32 0171}172 173; Make sure SCCP honors the xor "idiom"174; rdar://9956541175define i32 @test3() {176; CHECK-LABEL: @test3(177; CHECK-NEXT: [[T:%.*]] = xor i32 undef, undef178; CHECK-NEXT: ret i32 [[T]]179;180 %t = xor i32 undef, undef181 ret i32 %t182}183 184; Be conservative with FP ops185define double @test4(double %x) {186; CHECK-LABEL: @test4(187; CHECK-NEXT: [[T:%.*]] = fadd double [[X:%.*]], undef188; CHECK-NEXT: ret double [[T]]189;190 %t = fadd double %x, undef191 ret double %t192}193 194; Make sure casts produce a possible value195define i32 @test5() {196; CHECK-LABEL: @test5(197; CHECK-NEXT: [[T:%.*]] = sext i8 undef to i32198; CHECK-NEXT: ret i32 [[T]]199;200 %t = sext i8 undef to i32201 ret i32 %t202}203 204; Make sure ashr produces a possible value205define i32 @test6() {206; CHECK-LABEL: @test6(207; CHECK-NEXT: [[T:%.*]] = ashr i32 undef, 31208; CHECK-NEXT: ret i32 [[T]]209;210 %t = ashr i32 undef, 31211 ret i32 %t212}213 214; Make sure lshr produces a possible value215define i32 @test7() {216; CHECK-LABEL: @test7(217; CHECK-NEXT: [[T:%.*]] = lshr i32 undef, 31218; CHECK-NEXT: ret i32 [[T]]219;220 %t = lshr i32 undef, 31221 ret i32 %t222}223 224; icmp eq with undef simplifies to undef225define i1 @test8() {226; CHECK-LABEL: @test8(227; CHECK-NEXT: [[T:%.*]] = icmp eq i32 undef, -1228; CHECK-NEXT: ret i1 [[T]]229;230 %t = icmp eq i32 undef, -1231 ret i1 %t232}233 234; Make sure we don't conclude that relational comparisons simplify to undef235define i1 @test9() {236; CHECK-LABEL: @test9(237; CHECK-NEXT: [[T:%.*]] = icmp ugt i32 undef, -1238; CHECK-NEXT: ret i1 [[T]]239;240 %t = icmp ugt i32 undef, -1241 ret i1 %t242}243 244; Make sure we handle extractvalue245define i64 @test10() {246; CHECK-LABEL: @test10(247; CHECK-NEXT: entry:248; CHECK-NEXT: ret i64 undef249;250entry:251 %e = extractvalue { i64, i64 } undef, 1252 ret i64 %e253}254 255@GV = common global i32 0, align 4256 257define i32 @test11(i1 %tobool) {258; CHECK-LABEL: @test11(259; CHECK-NEXT: entry:260; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr @test11, @GV261; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[CMP]] to i32262; CHECK-NEXT: [[SHR4:%.*]] = ashr i32 undef, [[EXT]]263; CHECK-NEXT: ret i32 [[SHR4]]264;265entry:266 %cmp = icmp eq ptr @test11, @GV267 %ext = zext i1 %cmp to i32268 %shr4 = ashr i32 undef, %ext269 ret i32 %shr4270}271 272; Test unary ops273define double @test12(double %x) {274; CHECK-LABEL: @test12(275; CHECK-NEXT: [[T:%.*]] = fneg double undef276; CHECK-NEXT: ret double [[T]]277;278 %t = fneg double undef279 ret double %t280}281