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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64 -slp-threshold=-20 -slp-vectorize-hor=0 < %s | FileCheck %s3 4define i16 @foo(i16 %in1, i16 %in2) {5; CHECK-LABEL: define i16 @foo(6; CHECK-SAME: i16 [[IN1:%.*]], i16 [[IN2:%.*]]) {7; CHECK-NEXT:  entry:8; CHECK-NEXT:    [[ZEXT1_1:%.*]] = zext i16 [[IN1]] to i649; CHECK-NEXT:    [[ZEXT2_1:%.*]] = zext i16 [[IN2]] to i6410; CHECK-NEXT:    [[TMP10:%.*]] = mul nuw nsw i64 [[ZEXT2_1]], [[ZEXT1_1]]11; CHECK-NEXT:    [[AND1:%.*]] = and i64 [[TMP10]], 6553512; CHECK-NEXT:    [[TMP8:%.*]] = icmp ne i64 [[AND1]], 6553313; CHECK-NEXT:    [[ZEXT3_1:%.*]] = zext i1 [[TMP8]] to i1614; CHECK-NEXT:    [[CMP2_1:%.*]] = icmp ne i64 [[TMP10]], 19660515; CHECK-NEXT:    [[ZEXT4_1:%.*]] = zext i1 [[CMP2_1]] to i1616; CHECK-NEXT:    [[ADD1:%.*]] = add nuw nsw i16 [[ZEXT3_1]], [[ZEXT4_1]]17; CHECK-NEXT:    [[ZEXT1_2:%.*]] = zext i16 [[IN1]] to i6418; CHECK-NEXT:    [[ZEXT2_2:%.*]] = zext i16 [[IN2]] to i6419; CHECK-NEXT:    [[TMP13:%.*]] = mul nuw nsw i64 [[ZEXT2_2]], [[ZEXT1_2]]20; CHECK-NEXT:    [[AND2:%.*]] = and i64 [[TMP13]], 6553521; CHECK-NEXT:    [[TMP11:%.*]] = icmp ne i64 [[AND2]], 6553322; CHECK-NEXT:    [[ZEXT3_2:%.*]] = zext i1 [[TMP11]] to i1623; CHECK-NEXT:    [[CMP2_2:%.*]] = icmp ne i64 [[TMP13]], 19660524; CHECK-NEXT:    [[ZEXT4_2:%.*]] = zext i1 [[CMP2_2]] to i1625; CHECK-NEXT:    [[ADD2:%.*]] = add nuw nsw i16 [[ADD1]], [[ZEXT4_2]]26; CHECK-NEXT:    [[ADD3:%.*]] = add nuw nsw i16 [[ADD2]], [[ZEXT3_2]]27; CHECK-NEXT:    ret i16 [[ADD3]]28;29entry:30  %zext1_1 = zext i16 %in1 to i6431  %zext2_1 = zext i16 %in2 to i6432  %mul1 = mul nuw nsw i64 %zext2_1, %zext1_133  %and1 = and i64 %mul1, 6553534  %cmp1_1 = icmp ne i64 %and1, 6553335  %zext3_1 = zext i1 %cmp1_1 to i1636  %cmp2_1 = icmp ne i64 %mul1, 19660537  %zext4_1 = zext i1 %cmp2_1 to i1638  %add1 = add nuw nsw i16 %zext3_1, %zext4_139  %zext1_2 = zext i16 %in1 to i6440  %zext2_2 = zext i16 %in2 to i6441  %mul2 = mul nuw nsw i64 %zext2_2, %zext1_242  %and2 = and i64 %mul2, 6553543  %cmp1_2 = icmp ne i64 %and2, 6553344  %zext3_2 = zext i1 %cmp1_2 to i1645  %cmp2_2 = icmp ne i64 %mul2, 19660546  %zext4_2 = zext i1 %cmp2_2 to i1647  %add2 = add nuw nsw i16 %add1, %zext4_248  %add3 = add nuw nsw i16 %add2, %zext3_249  ret i16 %add350}51 52 53