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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define void @h() {5; CHECK-LABEL: define void @h() {6; CHECK-NEXT: entry:7; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 168; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 29; CHECK-NEXT: ret void10;11entry:12 %conv9 = zext i16 0 to i3213 %arrayidx2 = getelementptr i8, ptr null, i64 1614 %conv310 = zext i16 0 to i3215 %add4 = add i32 %conv310, %conv916 %sub = sub i32 0, %conv31017 %conv15 = sext i16 0 to i3218 %shr = ashr i32 0, 019 %arrayidx18 = getelementptr i8, ptr null, i64 2420 %conv19 = sext i16 0 to i3221 %sub20 = sub i32 %shr, %conv1922 %shr29 = ashr i32 0, 023 %add30 = add i32 %shr29, %conv1524 %sub39 = or i32 %sub, %sub2025 %conv40 = trunc i32 %sub39 to i1626 store i16 %conv40, ptr %arrayidx2, align 227 %sub44 = or i32 %add4, %add3028 %conv45 = trunc i32 %sub44 to i1629 store i16 %conv45, ptr %arrayidx18, align 230 %arrayidx2.1 = getelementptr i8, ptr null, i64 1831 %conv3.112 = zext i16 0 to i3232 %add4.1 = add i32 %conv3.112, 033 %sub.1 = sub i32 0, %conv3.11234 %conv15.1 = sext i16 0 to i3235 %shr.1 = ashr i32 0, 036 %arrayidx18.1 = getelementptr i8, ptr null, i64 2637 %conv19.1 = sext i16 0 to i3238 %sub20.1 = sub i32 %shr.1, %conv19.139 %shr29.1 = ashr i32 0, 040 %add30.1 = add i32 %shr29.1, %conv15.141 %sub39.1 = or i32 %sub.1, %sub20.142 %conv40.1 = trunc i32 %sub39.1 to i1643 store i16 %conv40.1, ptr %arrayidx2.1, align 244 %sub44.1 = or i32 %add4.1, %add30.145 %conv45.1 = trunc i32 %sub44.1 to i1646 store i16 %conv45.1, ptr %arrayidx18.1, align 247 %conv.213 = zext i16 0 to i3248 %arrayidx2.2 = getelementptr i8, ptr null, i64 2049 %conv3.214 = zext i16 0 to i3250 %add4.2 = add i32 0, %conv.21351 %sub.2 = sub i32 0, %conv3.21452 %conv15.2 = sext i16 0 to i3253 %shr.2 = ashr i32 0, 054 %arrayidx18.2 = getelementptr i8, ptr null, i64 2855 %conv19.2 = sext i16 0 to i3256 %sub20.2 = sub i32 %shr.2, %conv19.257 %shr29.2 = ashr i32 0, 058 %add30.2 = add i32 %shr29.2, %conv15.259 %sub39.2 = or i32 %sub.2, %sub20.260 %conv40.2 = trunc i32 %sub39.2 to i1661 store i16 %conv40.2, ptr %arrayidx2.2, align 262 %sub44.2 = or i32 %add4.2, %add30.263 %conv45.2 = trunc i32 %sub44.2 to i1664 store i16 %conv45.2, ptr %arrayidx18.2, align 265 %conv.315 = zext i16 0 to i3266 %arrayidx2.3 = getelementptr i8, ptr null, i64 2267 %conv3.316 = zext i16 0 to i3268 %add4.3 = add i32 0, %conv.31569 %sub.3 = sub i32 0, %conv3.31670 %conv15.3 = sext i16 0 to i3271 %shr.3 = ashr i32 0, 072 %arrayidx18.3 = getelementptr i8, ptr null, i64 3073 %conv19.3 = sext i16 0 to i3274 %sub20.3 = sub i32 %shr.3, %conv19.375 %shr29.3 = ashr i32 0, 076 %add30.3 = add i32 %shr29.3, %conv15.377 %sub39.3 = or i32 %sub.3, %sub20.378 %conv40.3 = trunc i32 %sub39.3 to i1679 store i16 %conv40.3, ptr %arrayidx2.3, align 280 %sub44.3 = or i32 %add4.3, %add30.381 %conv45.3 = trunc i32 %sub44.3 to i1682 store i16 %conv45.3, ptr %arrayidx18.3, align 283 ret void84}85