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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=slp-vectorizer -mtriple=aarch64--linux-gnu -mcpu=generic < %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5target triple = "aarch64"6 7%struct.weight_t = type { i32, i32 }8 9define void @f_noalias(ptr noalias nocapture %dst, ptr noalias nocapture readonly %src, ptr noalias nocapture readonly %w) {10; CHECK-LABEL: @f_noalias(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[W:%.*]], align 1613; CHECK-NEXT: [[OFFSET:%.*]] = getelementptr inbounds [[STRUCT_WEIGHT_T:%.*]], ptr [[W]], i64 0, i32 114; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[OFFSET]], align 415; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[SRC:%.*]], align 116; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>17; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 018; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <4 x i32> zeroinitializer19; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP5]], [[TMP3]]20; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 021; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> poison, <4 x i32> zeroinitializer22; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP8]]23; CHECK-NEXT: [[TMP10:%.*]] = icmp ult <4 x i32> [[TMP9]], splat (i32 256)24; CHECK-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[TMP9]], zeroinitializer25; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i1> [[TMP11]] to <4 x i32>26; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP9]], <4 x i32> [[TMP12]]27; CHECK-NEXT: [[TMP14:%.*]] = trunc <4 x i32> [[TMP13]] to <4 x i8>28; CHECK-NEXT: store <4 x i8> [[TMP14]], ptr [[DST:%.*]], align 129; CHECK-NEXT: ret void30;31entry:32 %0 = load i32, ptr %w, align 1633 %offset = getelementptr inbounds %struct.weight_t, ptr %w, i64 0, i32 134 %1 = load i32, ptr %offset, align 435 %2 = load i8, ptr %src, align 136 %conv = zext i8 %2 to i3237 %mul = mul nsw i32 %0, %conv38 %add = add nsw i32 %mul, %139 %tobool.not.i = icmp ult i32 %add, 25640 %3 = icmp sgt i32 %add, 041 %shr.i = sext i1 %3 to i3242 %cond.i = select i1 %tobool.not.i, i32 %add, i32 %shr.i43 %conv.i = trunc i32 %cond.i to i844 store i8 %conv.i, ptr %dst, align 145 %arrayidx.1 = getelementptr inbounds i8, ptr %src, i64 146 %4 = load i8, ptr %arrayidx.1, align 147 %conv.1 = zext i8 %4 to i3248 %mul.1 = mul nsw i32 %0, %conv.149 %add.1 = add nsw i32 %mul.1, %150 %tobool.not.i.1 = icmp ult i32 %add.1, 25651 %5 = icmp sgt i32 %add.1, 052 %shr.i.1 = sext i1 %5 to i3253 %cond.i.1 = select i1 %tobool.not.i.1, i32 %add.1, i32 %shr.i.154 %conv.i.1 = trunc i32 %cond.i.1 to i855 %arrayidx2.1 = getelementptr inbounds i8, ptr %dst, i64 156 store i8 %conv.i.1, ptr %arrayidx2.1, align 157 %arrayidx.2 = getelementptr inbounds i8, ptr %src, i64 258 %6 = load i8, ptr %arrayidx.2, align 159 %conv.2 = zext i8 %6 to i3260 %mul.2 = mul nsw i32 %0, %conv.261 %add.2 = add nsw i32 %mul.2, %162 %tobool.not.i.2 = icmp ult i32 %add.2, 25663 %7 = icmp sgt i32 %add.2, 064 %shr.i.2 = sext i1 %7 to i3265 %cond.i.2 = select i1 %tobool.not.i.2, i32 %add.2, i32 %shr.i.266 %conv.i.2 = trunc i32 %cond.i.2 to i867 %arrayidx2.2 = getelementptr inbounds i8, ptr %dst, i64 268 store i8 %conv.i.2, ptr %arrayidx2.2, align 169 %arrayidx.3 = getelementptr inbounds i8, ptr %src, i64 370 %8 = load i8, ptr %arrayidx.3, align 171 %conv.3 = zext i8 %8 to i3272 %mul.3 = mul nsw i32 %0, %conv.373 %add.3 = add nsw i32 %mul.3, %174 %tobool.not.i.3 = icmp ult i32 %add.3, 25675 %9 = icmp sgt i32 %add.3, 076 %shr.i.3 = sext i1 %9 to i3277 %cond.i.3 = select i1 %tobool.not.i.3, i32 %add.3, i32 %shr.i.378 %conv.i.3 = trunc i32 %cond.i.3 to i879 %arrayidx2.3 = getelementptr inbounds i8, ptr %dst, i64 380 store i8 %conv.i.3, ptr %arrayidx2.3, align 181 ret void82}83 84; This is the same test as above, expect that the pointers don't have 'noalias'.85; This currently prevents SLP vectorization, but the SLP vectorizer should86; be taught to emit runtime checks enabling vectorization.87;88define void @f_alias(ptr nocapture %dst, ptr nocapture readonly %src, ptr nocapture readonly %w) {89; CHECK-LABEL: @f_alias(90; CHECK-NEXT: entry:91; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[W:%.*]], align 1692; CHECK-NEXT: [[OFFSET:%.*]] = getelementptr inbounds [[STRUCT_WEIGHT_T:%.*]], ptr [[W]], i64 0, i32 193; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[OFFSET]], align 494; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[SRC:%.*]], align 195; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP2]] to i3296; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0]], [[CONV]]97; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL]], [[TMP1]]98; CHECK-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp ult i32 [[ADD]], 25699; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[ADD]], 0100; CHECK-NEXT: [[SHR_I:%.*]] = sext i1 [[TMP3]] to i32101; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[TOBOOL_NOT_I]], i32 [[ADD]], i32 [[SHR_I]]102; CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[COND_I]] to i8103; CHECK-NEXT: store i8 [[CONV_I]], ptr [[DST:%.*]], align 1104; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 1105; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[ARRAYIDX_1]], align 1106; CHECK-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP4]] to i32107; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP0]], [[CONV_1]]108; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[MUL_1]], [[TMP1]]109; CHECK-NEXT: [[TOBOOL_NOT_I_1:%.*]] = icmp ult i32 [[ADD_1]], 256110; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[ADD_1]], 0111; CHECK-NEXT: [[SHR_I_1:%.*]] = sext i1 [[TMP5]] to i32112; CHECK-NEXT: [[COND_I_1:%.*]] = select i1 [[TOBOOL_NOT_I_1]], i32 [[ADD_1]], i32 [[SHR_I_1]]113; CHECK-NEXT: [[CONV_I_1:%.*]] = trunc i32 [[COND_I_1]] to i8114; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 1115; CHECK-NEXT: store i8 [[CONV_I_1]], ptr [[ARRAYIDX2_1]], align 1116; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 2117; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX_2]], align 1118; CHECK-NEXT: [[CONV_2:%.*]] = zext i8 [[TMP6]] to i32119; CHECK-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[TMP0]], [[CONV_2]]120; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[MUL_2]], [[TMP1]]121; CHECK-NEXT: [[TOBOOL_NOT_I_2:%.*]] = icmp ult i32 [[ADD_2]], 256122; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[ADD_2]], 0123; CHECK-NEXT: [[SHR_I_2:%.*]] = sext i1 [[TMP7]] to i32124; CHECK-NEXT: [[COND_I_2:%.*]] = select i1 [[TOBOOL_NOT_I_2]], i32 [[ADD_2]], i32 [[SHR_I_2]]125; CHECK-NEXT: [[CONV_I_2:%.*]] = trunc i32 [[COND_I_2]] to i8126; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 2127; CHECK-NEXT: store i8 [[CONV_I_2]], ptr [[ARRAYIDX2_2]], align 1128; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 3129; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[ARRAYIDX_3]], align 1130; CHECK-NEXT: [[CONV_3:%.*]] = zext i8 [[TMP8]] to i32131; CHECK-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP0]], [[CONV_3]]132; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[MUL_3]], [[TMP1]]133; CHECK-NEXT: [[TOBOOL_NOT_I_3:%.*]] = icmp ult i32 [[ADD_3]], 256134; CHECK-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[ADD_3]], 0135; CHECK-NEXT: [[SHR_I_3:%.*]] = sext i1 [[TMP9]] to i32136; CHECK-NEXT: [[COND_I_3:%.*]] = select i1 [[TOBOOL_NOT_I_3]], i32 [[ADD_3]], i32 [[SHR_I_3]]137; CHECK-NEXT: [[CONV_I_3:%.*]] = trunc i32 [[COND_I_3]] to i8138; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 3139; CHECK-NEXT: store i8 [[CONV_I_3]], ptr [[ARRAYIDX2_3]], align 1140; CHECK-NEXT: ret void141;142entry:143 %0 = load i32, ptr %w, align 16144 %offset = getelementptr inbounds %struct.weight_t, ptr %w, i64 0, i32 1145 %1 = load i32, ptr %offset, align 4146 %2 = load i8, ptr %src, align 1147 %conv = zext i8 %2 to i32148 %mul = mul nsw i32 %0, %conv149 %add = add nsw i32 %mul, %1150 %tobool.not.i = icmp ult i32 %add, 256151 %3 = icmp sgt i32 %add, 0152 %shr.i = sext i1 %3 to i32153 %cond.i = select i1 %tobool.not.i, i32 %add, i32 %shr.i154 %conv.i = trunc i32 %cond.i to i8155 store i8 %conv.i, ptr %dst, align 1156 %arrayidx.1 = getelementptr inbounds i8, ptr %src, i64 1157 %4 = load i8, ptr %arrayidx.1, align 1158 %conv.1 = zext i8 %4 to i32159 %mul.1 = mul nsw i32 %0, %conv.1160 %add.1 = add nsw i32 %mul.1, %1161 %tobool.not.i.1 = icmp ult i32 %add.1, 256162 %5 = icmp sgt i32 %add.1, 0163 %shr.i.1 = sext i1 %5 to i32164 %cond.i.1 = select i1 %tobool.not.i.1, i32 %add.1, i32 %shr.i.1165 %conv.i.1 = trunc i32 %cond.i.1 to i8166 %arrayidx2.1 = getelementptr inbounds i8, ptr %dst, i64 1167 store i8 %conv.i.1, ptr %arrayidx2.1, align 1168 %arrayidx.2 = getelementptr inbounds i8, ptr %src, i64 2169 %6 = load i8, ptr %arrayidx.2, align 1170 %conv.2 = zext i8 %6 to i32171 %mul.2 = mul nsw i32 %0, %conv.2172 %add.2 = add nsw i32 %mul.2, %1173 %tobool.not.i.2 = icmp ult i32 %add.2, 256174 %7 = icmp sgt i32 %add.2, 0175 %shr.i.2 = sext i1 %7 to i32176 %cond.i.2 = select i1 %tobool.not.i.2, i32 %add.2, i32 %shr.i.2177 %conv.i.2 = trunc i32 %cond.i.2 to i8178 %arrayidx2.2 = getelementptr inbounds i8, ptr %dst, i64 2179 store i8 %conv.i.2, ptr %arrayidx2.2, align 1180 %arrayidx.3 = getelementptr inbounds i8, ptr %src, i64 3181 %8 = load i8, ptr %arrayidx.3, align 1182 %conv.3 = zext i8 %8 to i32183 %mul.3 = mul nsw i32 %0, %conv.3184 %add.3 = add nsw i32 %mul.3, %1185 %tobool.not.i.3 = icmp ult i32 %add.3, 256186 %9 = icmp sgt i32 %add.3, 0187 %shr.i.3 = sext i1 %9 to i32188 %cond.i.3 = select i1 %tobool.not.i.3, i32 %add.3, i32 %shr.i.3189 %conv.i.3 = trunc i32 %cond.i.3 to i8190 %arrayidx2.3 = getelementptr inbounds i8, ptr %dst, i64 3191 store i8 %conv.i.3, ptr %arrayidx2.3, align 1192 ret void193}194