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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define double @test(ptr %0, ptr %1) {5; CHECK-LABEL: define double @test(6; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 1449; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP1]], i64 23210; CHECK-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr [[TMP2]], align 811; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 812; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP3]], align 813; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP1]], align 814; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP0]], align 815; CHECK-NEXT: [[TMP9:%.*]] = fmul reassoc nsz <4 x double> [[TMP4]], splat (double 1.000000e+00)16; CHECK-NEXT: [[TMP10:%.*]] = call reassoc nsz double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP9]])17; CHECK-NEXT: [[TMP11:%.*]] = fmul double [[TMP5]], 2.000000e+0018; CHECK-NEXT: [[OP_RDX5:%.*]] = fadd reassoc nsz double [[TMP11]], [[TMP8]]19; CHECK-NEXT: [[OP_RDX6:%.*]] = fadd reassoc nsz double [[OP_RDX5]], [[TMP6]]20; CHECK-NEXT: [[OP_RDX7:%.*]] = fadd reassoc nsz double [[OP_RDX6]], [[TMP7]]21; CHECK-NEXT: [[OP_RDX8:%.*]] = fadd reassoc nsz double [[OP_RDX7]], [[TMP10]]22; CHECK-NEXT: ret double [[OP_RDX8]]23;24entry:25 %2 = getelementptr i8, ptr %1, i64 14426 %3 = getelementptr i8, ptr %1, i64 15227 %4 = getelementptr i8, ptr %1, i64 16028 %5 = getelementptr i8, ptr %1, i64 16829 %6 = getelementptr i8, ptr %1, i64 23230 %7 = load double, ptr %2, align 831 %8 = load double, ptr %3, align 832 %9 = fadd reassoc nsz double %8, %733 %10 = load double, ptr %4, align 834 %11 = fadd reassoc nsz double %10, %935 %12 = load double, ptr %5, align 836 %13 = fadd reassoc nsz double %12, %1137 %14 = load double, ptr %0, align 838 %15 = fadd reassoc nsz double %14, %1339 %16 = fadd reassoc nsz double %14, %1540 %17 = load double, ptr %6, align 841 %18 = fadd reassoc nsz double %17, %1642 %19 = load double, ptr %1, align 843 %20 = fadd reassoc nsz double %19, %1844 %21 = load double, ptr %0, align 845 %22 = fadd reassoc nsz double %21, %2046 ret double %2247}48