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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 6; This test is reduced from the matrix multiplication benchmark in the test-suite:7; https://github.com/llvm/llvm-test-suite/tree/main/SingleSource/Benchmarks/Misc/matmul_f64_4x4.c8; The operations here are expected to be vectorized to <2 x double>.9; Otherwise, performance will suffer on Cortex-A53.10 11define void @wrap_mul4(ptr nocapture %Out, ptr nocapture readonly %A, ptr nocapture readonly %B) {12; CHECK-LABEL: @wrap_mul4(13; CHECK-NEXT: [[TEMP:%.*]] = load double, ptr [[A:%.*]], align 814; CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 0, i64 115; CHECK-NEXT: [[TEMP2:%.*]] = load double, ptr [[ARRAYIDX5_I]], align 816; CHECK-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B:%.*]], i64 1, i64 017; CHECK-NEXT: [[ARRAYIDX25_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 0, i64 218; CHECK-NEXT: [[ARRAYIDX30_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 1, i64 219; CHECK-NEXT: [[ARRAYIDX47_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 020; CHECK-NEXT: [[TEMP10:%.*]] = load double, ptr [[ARRAYIDX47_I]], align 821; CHECK-NEXT: [[ARRAYIDX52_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 122; CHECK-NEXT: [[TEMP11:%.*]] = load double, ptr [[ARRAYIDX52_I]], align 823; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[B]], align 824; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TEMP]], i32 025; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer26; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP1]]27; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr [[ARRAYIDX7_I]], align 828; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TEMP2]], i32 029; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <2 x i32> zeroinitializer30; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], [[TMP5]]31; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP4]], [[TMP8]]32; CHECK-NEXT: [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4:%.*]] = getelementptr inbounds double, ptr [[OUT:%.*]], i64 233; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[ARRAYIDX25_I]], align 834; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP3]], [[TMP10]]35; CHECK-NEXT: [[TMP12:%.*]] = load <2 x double>, ptr [[ARRAYIDX30_I]], align 836; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x double> [[TMP7]], [[TMP12]]37; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[TMP11]], [[TMP13]]38; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[OUT]], align 839; CHECK-NEXT: store <2 x double> [[TMP14]], ptr [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4]], align 840; CHECK-NEXT: [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 441; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x double> poison, double [[TEMP10]], i32 042; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x double> [[TMP15]], <2 x double> poison, <2 x i32> zeroinitializer43; CHECK-NEXT: [[TMP17:%.*]] = fmul <2 x double> [[TMP1]], [[TMP16]]44; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x double> poison, double [[TEMP11]], i32 045; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x double> [[TMP18]], <2 x double> poison, <2 x i32> zeroinitializer46; CHECK-NEXT: [[TMP20:%.*]] = fmul <2 x double> [[TMP5]], [[TMP19]]47; CHECK-NEXT: [[TMP21:%.*]] = fadd <2 x double> [[TMP17]], [[TMP20]]48; CHECK-NEXT: store <2 x double> [[TMP21]], ptr [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8]], align 849; CHECK-NEXT: [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 650; CHECK-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP10]], [[TMP16]]51; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> [[TMP12]], [[TMP19]]52; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP22]], [[TMP23]]53; CHECK-NEXT: store <2 x double> [[TMP24]], ptr [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12]], align 854; CHECK-NEXT: ret void55;56 %temp = load double, ptr %A, align 857 %temp1 = load double, ptr %B, align 858 %mul.i = fmul double %temp, %temp159 %arrayidx5.i = getelementptr inbounds [2 x double], ptr %A, i64 0, i64 160 %temp2 = load double, ptr %arrayidx5.i, align 861 %arrayidx7.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 062 %temp3 = load double, ptr %arrayidx7.i, align 863 %mul8.i = fmul double %temp2, %temp364 %add.i = fadd double %mul.i, %mul8.i65 %arrayidx13.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 166 %temp4 = load double, ptr %arrayidx13.i, align 867 %mul14.i = fmul double %temp, %temp468 %arrayidx18.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 169 %temp5 = load double, ptr %arrayidx18.i, align 870 %mul19.i = fmul double %temp2, %temp571 %add20.i = fadd double %mul14.i, %mul19.i72 %arrayidx25.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 273 %temp6 = load double, ptr %arrayidx25.i, align 874 %mul26.i = fmul double %temp, %temp675 %arrayidx30.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 276 %temp7 = load double, ptr %arrayidx30.i, align 877 %mul31.i = fmul double %temp2, %temp778 %add32.i = fadd double %mul26.i, %mul31.i79 %arrayidx37.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 380 %temp8 = load double, ptr %arrayidx37.i, align 881 %mul38.i = fmul double %temp, %temp882 %arrayidx42.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 383 %temp9 = load double, ptr %arrayidx42.i, align 884 %mul43.i = fmul double %temp2, %temp985 %add44.i = fadd double %mul38.i, %mul43.i86 %arrayidx47.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 087 %temp10 = load double, ptr %arrayidx47.i, align 888 %mul50.i = fmul double %temp1, %temp1089 %arrayidx52.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 190 %temp11 = load double, ptr %arrayidx52.i, align 891 %mul55.i = fmul double %temp3, %temp1192 %add56.i = fadd double %mul50.i, %mul55.i93 %mul62.i = fmul double %temp4, %temp1094 %mul67.i = fmul double %temp5, %temp1195 %add68.i = fadd double %mul62.i, %mul67.i96 %mul74.i = fmul double %temp6, %temp1097 %mul79.i = fmul double %temp7, %temp1198 %add80.i = fadd double %mul74.i, %mul79.i99 %mul86.i = fmul double %temp8, %temp10100 %mul91.i = fmul double %temp9, %temp11101 %add92.i = fadd double %mul86.i, %mul91.i102 store double %add.i, ptr %Out, align 8103 %Res.i.sroa.4.0.Out2.i.sroa_idx2 = getelementptr inbounds double, ptr %Out, i64 1104 store double %add20.i, ptr %Res.i.sroa.4.0.Out2.i.sroa_idx2, align 8105 %Res.i.sroa.5.0.Out2.i.sroa_idx4 = getelementptr inbounds double, ptr %Out, i64 2106 store double %add32.i, ptr %Res.i.sroa.5.0.Out2.i.sroa_idx4, align 8107 %Res.i.sroa.6.0.Out2.i.sroa_idx6 = getelementptr inbounds double, ptr %Out, i64 3108 store double %add44.i, ptr %Res.i.sroa.6.0.Out2.i.sroa_idx6, align 8109 %Res.i.sroa.7.0.Out2.i.sroa_idx8 = getelementptr inbounds double, ptr %Out, i64 4110 store double %add56.i, ptr %Res.i.sroa.7.0.Out2.i.sroa_idx8, align 8111 %Res.i.sroa.8.0.Out2.i.sroa_idx10 = getelementptr inbounds double, ptr %Out, i64 5112 store double %add68.i, ptr %Res.i.sroa.8.0.Out2.i.sroa_idx10, align 8113 %Res.i.sroa.9.0.Out2.i.sroa_idx12 = getelementptr inbounds double, ptr %Out, i64 6114 store double %add80.i, ptr %Res.i.sroa.9.0.Out2.i.sroa_idx12, align 8115 %Res.i.sroa.10.0.Out2.i.sroa_idx14 = getelementptr inbounds double, ptr %Out, i64 7116 store double %add92.i, ptr %Res.i.sroa.10.0.Out2.i.sroa_idx14, align 8117 ret void118}119 120