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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s3 4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"5target triple = "aarch64--linux-gnu"6 7; This test ensures that we do not regress due to PR26364. The vectorizer8; should not compute a smaller size for %k.13 since it is in a use-def cycle9; and cannot be demoted.10;11define fastcc void @PR26364(i1 %arg) {12; CHECK-LABEL: @PR26364(13; CHECK-NEXT: entry:14; CHECK-NEXT: br i1 %arg, label [[FOR_END11:%.*]], label [[FOR_COND4:%.*]]15; CHECK: for.cond4:16; CHECK-NEXT: [[K_13:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[K_3:%.*]], [[FOR_COND4]] ]17; CHECK-NEXT: [[E_02:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ 0, [[FOR_COND4]] ]18; CHECK-NEXT: [[E_1:%.*]] = select i1 undef, i32 [[E_02]], i32 019; CHECK-NEXT: [[K_3]] = select i1 undef, i32 [[K_13]], i32 undef20; CHECK-NEXT: br label [[FOR_COND4]]21; CHECK: for.end11:22; CHECK-NEXT: ret void23;24entry:25 br i1 %arg, label %for.end11, label %for.cond426 27for.cond4:28 %k.13 = phi i32 [ undef, %entry ], [ %k.3, %for.cond4 ]29 %e.02 = phi i32 [ 1, %entry ], [ 0, %for.cond4 ]30 %e.1 = select i1 undef, i32 %e.02, i32 031 %k.3 = select i1 undef, i32 %k.13, i32 undef32 br label %for.cond433 34for.end11:35 ret void36}37 38; This test ensures that we do not regress due to PR26629. We must look at39; every root in the vectorizable tree when computing minimum sizes since one40; root may require fewer bits than another.41;42define void @PR26629(ptr %c, i1 %arg) {43; CHECK-LABEL: @PR26629(44; CHECK-NEXT: entry:45; CHECK-NEXT: br i1 %arg, label [[FOR_PH:%.*]], label [[FOR_END:%.*]]46; CHECK: for.ph:47; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[C:%.*]], align 448; CHECK-NEXT: br label [[FOR_BODY:%.*]]49; CHECK: for.body:50; CHECK-NEXT: [[D:%.*]] = phi i72 [ 576507472957710340, [[FOR_PH]] ], [ [[BF_SET17:%.*]], [[FOR_BODY]] ]51; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP0]], undef52; CHECK-NEXT: [[BF_CLEAR13:%.*]] = and i72 [[D]], -57646074800846438453; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[SUB]] to i7254; CHECK-NEXT: [[BF_VALUE15:%.*]] = and i72 [[TMP1]], 819155; CHECK-NEXT: [[BF_CLEAR16:%.*]] = or i72 [[BF_VALUE15]], [[BF_CLEAR13]]56; CHECK-NEXT: [[BF_SET17]] = or i72 [[BF_CLEAR16]], undef57; CHECK-NEXT: br label [[FOR_BODY]]58; CHECK: for.end:59; CHECK-NEXT: ret void60;61entry:62 br i1 %arg, label %for.ph, label %for.end63 64for.ph:65 %0 = load i32, ptr %c, align 466 br label %for.body67 68for.body:69 %d = phi i72 [ 576507472957710340, %for.ph ], [ %bf.set17, %for.body ]70 %sub = sub i32 %0, undef71 %bf.clear13 = and i72 %d, -57646074800846438472 %1 = zext i32 %sub to i7273 %bf.value15 = and i72 %1, 819174 %bf.clear16 = or i72 %bf.value15, %bf.clear1375 %bf.set17 = or i72 %bf.clear16, undef76 br label %for.body77 78for.end:79 ret void80}81