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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-w32-windows-gnu | FileCheck %s3 4define i32 @foo(i32 %v1, double %v2, i1 %arg, i32 %arg2) {5; CHECK-LABEL: @foo(6; CHECK-NEXT: entry:7; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[V1:%.*]], i32 08; CHECK-NEXT: [[TMP1:%.*]] = sitofp <2 x i32> [[TMP0]] to <2 x double>9; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>10; CHECK-NEXT: br label [[FOR_COND15_PREHEADER:%.*]]11; CHECK: for.cond15.preheader:12; CHECK-NEXT: br label [[IF_END:%.*]]13; CHECK: for.cond15:14; CHECK-NEXT: br label [[IF_END_1:%.*]]15; CHECK: if.end:16; CHECK-NEXT: br label [[FOR_COND15:%.*]]17; CHECK: for.end39:18; CHECK-NEXT: switch i32 [[ARG2:%.*]], label [[DO_BODY:%.*]] [19; CHECK-NEXT: i32 0, label [[SW_BB:%.*]]20; CHECK-NEXT: i32 1, label [[SW_BB195:%.*]]21; CHECK-NEXT: ]22; CHECK: sw.bb:23; CHECK-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 1, i64 024; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[V2:%.*]], i32 025; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP1]]26; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>27; CHECK-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr [[ARRAYIDX43]], align 828; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x double> [[TMP6]], [[TMP5]]29; CHECK-NEXT: [[TMP9:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> undef, <4 x double> [[TMP2]], <4 x double> [[TMP7]])30; CHECK-NEXT: br label [[SW_EPILOG:%.*]]31; CHECK: sw.bb195:32; CHECK-NEXT: br label [[SW_EPILOG]]33; CHECK: do.body:34; CHECK-NEXT: unreachable35; CHECK: sw.epilog:36; CHECK-NEXT: [[TMP10:%.*]] = phi <4 x double> [ undef, [[SW_BB195]] ], [ [[TMP9]], [[SW_BB]] ]37; CHECK-NEXT: ret i32 undef38; CHECK: if.end.1:39; CHECK-NEXT: br label [[FOR_COND15_1:%.*]]40; CHECK: for.cond15.1:41; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_END39:%.*]], label [[FOR_COND15_PREHEADER]]42;43entry:44 %conv = sitofp i32 undef to double45 %conv2 = sitofp i32 %v1 to double46 br label %for.cond15.preheader47 48for.cond15.preheader: ; preds = %for.cond15.1, %entry49 br label %if.end50 51for.cond15: ; preds = %if.end52 br label %if.end.153 54if.end: ; preds = %for.cond15.preheader55 br label %for.cond1556 57for.end39: ; preds = %for.cond15.158 switch i32 %arg2, label %do.body [59 i32 0, label %sw.bb60 i32 1, label %sw.bb19561 ]62 63sw.bb: ; preds = %for.end3964 %arrayidx43 = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 1, i64 065 %0 = load double, ptr %arrayidx43, align 866 %arrayidx45 = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 2, i64 067 %1 = load double, ptr %arrayidx45, align 868 %arrayidx51 = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 2, i64 169 %2 = load double, ptr %arrayidx51, align 870 %arrayidx58 = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 1, i64 171 %3 = load double, ptr %arrayidx58, align 872 %mul = fmul double %v2, %conv273 %mul109 = fmul double undef, %conv74 %mul143 = fmul double %0, %mul75 %4 = call double @llvm.fmuladd.f64(double undef, double %conv2, double %mul143)76 %mul154 = fmul double %1, %mul10977 %5 = call double @llvm.fmuladd.f64(double undef, double %conv, double %mul154)78 %mul172 = fmul double %3, %mul79 %6 = call double @llvm.fmuladd.f64(double undef, double %conv2, double %mul172)80 %mul183 = fmul double %2, %mul10981 %7 = call double @llvm.fmuladd.f64(double undef, double %conv, double %mul183)82 br label %sw.epilog83 84sw.bb195: ; preds = %for.end3985 br label %sw.epilog86 87do.body: ; preds = %for.end3988 unreachable89 90sw.epilog: ; preds = %sw.bb195, %sw.bb91 %x4.0 = phi double [ undef, %sw.bb195 ], [ %7, %sw.bb ]92 %x3.0 = phi double [ undef, %sw.bb195 ], [ %6, %sw.bb ]93 %x1.0 = phi double [ undef, %sw.bb195 ], [ %5, %sw.bb ]94 %x0.0 = phi double [ undef, %sw.bb195 ], [ %4, %sw.bb ]95 ret i32 undef96 97if.end.1: ; preds = %for.cond1598 br label %for.cond15.199 100for.cond15.1: ; preds = %if.end.1101 br i1 %arg, label %for.end39, label %for.cond15.preheader102}103 104declare double @llvm.fmuladd.f64(double, double, double)105