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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5target triple = "aarch64--linux-gnu"6 7define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {8; CHECK-LABEL: @build_vec_v2i64(9; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[V0:%.*]], [[V1:%.*]]10; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i64> [[V0]], [[V1]]11; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> <i32 1, i32 2>12; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> <i32 0, i32 3>13; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP3]]14; CHECK-NEXT: ret <2 x i64> [[TMP5]]15;16 %v0.0 = extractelement <2 x i64> %v0, i32 017 %v0.1 = extractelement <2 x i64> %v0, i32 118 %v1.0 = extractelement <2 x i64> %v1, i32 019 %v1.1 = extractelement <2 x i64> %v1, i32 120 %tmp0.0 = add i64 %v0.0, %v1.021 %tmp0.1 = add i64 %v0.1, %v1.122 %tmp1.0 = sub i64 %v0.0, %v1.023 %tmp1.1 = sub i64 %v0.1, %v1.124 %tmp2.0 = add i64 %tmp0.0, %tmp0.125 %tmp2.1 = add i64 %tmp1.0, %tmp1.126 %tmp3.0 = insertelement <2 x i64> undef, i64 %tmp2.0, i32 027 %tmp3.1 = insertelement <2 x i64> %tmp3.0, i64 %tmp2.1, i32 128 ret <2 x i64> %tmp3.129}30 31define void @store_chain_v2i64(ptr %a, ptr %b, ptr %c) {32; CHECK-LABEL: @store_chain_v2i64(33; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 834; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B:%.*]], align 835; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]]36; CHECK-NEXT: [[TMP4:%.*]] = sub <2 x i64> [[TMP1]], [[TMP2]]37; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> <i32 1, i32 2>38; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> <i32 0, i32 3>39; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[TMP6]], [[TMP5]]40; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[C:%.*]], align 841; CHECK-NEXT: ret void42;43 %a.1 = getelementptr i64, ptr %a, i64 144 %b.1 = getelementptr i64, ptr %b, i64 145 %c.1 = getelementptr i64, ptr %c, i64 146 %v0.0 = load i64, ptr %a, align 847 %v0.1 = load i64, ptr %a.1, align 848 %v1.0 = load i64, ptr %b, align 849 %v1.1 = load i64, ptr %b.1, align 850 %tmp0.0 = add i64 %v0.0, %v1.051 %tmp0.1 = add i64 %v0.1, %v1.152 %tmp1.0 = sub i64 %v0.0, %v1.053 %tmp1.1 = sub i64 %v0.1, %v1.154 %tmp2.0 = add i64 %tmp0.0, %tmp0.155 %tmp2.1 = add i64 %tmp1.0, %tmp1.156 store i64 %tmp2.0, ptr %c, align 857 store i64 %tmp2.1, ptr %c.1, align 858 ret void59}60 61define <4 x i32> @build_vec_v4i32(<4 x i32> %v0, <4 x i32> %v1) {62; CHECK-LABEL: @build_vec_v4i32(63; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], [[V1:%.*]]64; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[V0]], [[V1]]65; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>66; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 1, i32 4, i32 7, i32 2>67; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP4]], [[TMP3]]68; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 3, i32 2>69; CHECK-NEXT: ret <4 x i32> [[TMP6]]70;71 %v0.0 = extractelement <4 x i32> %v0, i32 072 %v0.1 = extractelement <4 x i32> %v0, i32 173 %v0.2 = extractelement <4 x i32> %v0, i32 274 %v0.3 = extractelement <4 x i32> %v0, i32 375 %v1.0 = extractelement <4 x i32> %v1, i32 076 %v1.1 = extractelement <4 x i32> %v1, i32 177 %v1.2 = extractelement <4 x i32> %v1, i32 278 %v1.3 = extractelement <4 x i32> %v1, i32 379 %tmp0.0 = add i32 %v0.0, %v1.080 %tmp0.1 = add i32 %v0.1, %v1.181 %tmp0.2 = add i32 %v0.2, %v1.282 %tmp0.3 = add i32 %v0.3, %v1.383 %tmp1.0 = sub i32 %v0.0, %v1.084 %tmp1.1 = sub i32 %v0.1, %v1.185 %tmp1.2 = sub i32 %v0.2, %v1.286 %tmp1.3 = sub i32 %v0.3, %v1.387 %tmp2.0 = add i32 %tmp0.0, %tmp0.188 %tmp2.1 = add i32 %tmp1.0, %tmp1.189 %tmp2.2 = add i32 %tmp0.2, %tmp0.390 %tmp2.3 = add i32 %tmp1.2, %tmp1.391 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 092 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 193 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 294 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 395 ret <4 x i32> %tmp3.396}97 98define <4 x i32> @build_vec_v4i32_reuse_0(<2 x i32> %v0, <2 x i32> %v1) {99; CHECK-LABEL: @build_vec_v4i32_reuse_0(100; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[V0:%.*]], [[V1:%.*]]101; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i32> [[V0]], [[V1]]102; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 1, i32 2>103; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 0, i32 3>104; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP4]], [[TMP3]]105; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>106; CHECK-NEXT: ret <4 x i32> [[TMP6]]107;108 %v0.0 = extractelement <2 x i32> %v0, i32 0109 %v0.1 = extractelement <2 x i32> %v0, i32 1110 %v1.0 = extractelement <2 x i32> %v1, i32 0111 %v1.1 = extractelement <2 x i32> %v1, i32 1112 %tmp0.0 = add i32 %v0.0, %v1.0113 %tmp0.1 = add i32 %v0.1, %v1.1114 %tmp1.0 = sub i32 %v0.0, %v1.0115 %tmp1.1 = sub i32 %v0.1, %v1.1116 %tmp2.0 = add i32 %tmp0.0, %tmp0.1117 %tmp2.1 = add i32 %tmp1.0, %tmp1.1118 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0119 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1120 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.0, i32 2121 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.1, i32 3122 ret <4 x i32> %tmp3.3123}124 125define <4 x i32> @build_vec_v4i32_reuse_1(<2 x i32> %v0, <2 x i32> %v1) {126; CHECK-LABEL: @build_vec_v4i32_reuse_1(127; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>128; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[V1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>129; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[TMP6]], [[TMP7]]130; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP6]], [[TMP7]]131; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>132; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[V0]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 0>133; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[V1]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 0>134; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]135; CHECK-NEXT: [[TMP11:%.*]] = xor <4 x i32> [[TMP1]], [[TMP2]]136; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>137; CHECK-NEXT: [[TMP9:%.*]] = sub <4 x i32> [[TMP5]], [[TMP10]]138; CHECK-NEXT: ret <4 x i32> [[TMP9]]139;140 %v0.0 = extractelement <2 x i32> %v0, i32 0141 %v0.1 = extractelement <2 x i32> %v0, i32 1142 %v1.0 = extractelement <2 x i32> %v1, i32 0143 %v1.1 = extractelement <2 x i32> %v1, i32 1144 %tmp0.0 = add i32 %v0.0, %v1.0145 %tmp0.1 = add i32 %v0.1, %v1.1146 %tmp0.2 = xor i32 %v0.0, %v1.0147 %tmp0.3 = xor i32 %v0.1, %v1.1148 %tmp1.0 = sub i32 %tmp0.0, %tmp0.1149 %tmp1.1 = sub i32 %tmp0.0, %tmp0.1150 %tmp1.2 = sub i32 %tmp0.2, %tmp0.3151 %tmp1.3 = sub i32 %tmp0.3, %tmp0.2152 %tmp2.0 = insertelement <4 x i32> undef, i32 %tmp1.0, i32 0153 %tmp2.1 = insertelement <4 x i32> %tmp2.0, i32 %tmp1.1, i32 1154 %tmp2.2 = insertelement <4 x i32> %tmp2.1, i32 %tmp1.2, i32 2155 %tmp2.3 = insertelement <4 x i32> %tmp2.2, i32 %tmp1.3, i32 3156 ret <4 x i32> %tmp2.3157}158 159define <4 x i32> @build_vec_v4i32_3_binops(<2 x i32> %v0, <2 x i32> %v1) {160; CHECK-LABEL: @build_vec_v4i32_3_binops(161; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[V0:%.*]], [[V1:%.*]]162; CHECK-NEXT: [[TMP2:%.*]] = mul <2 x i32> [[V0]], [[V1]]163; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 1, i32 2>164; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 0, i32 3>165; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP4]], [[TMP3]]166; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i32> [[V0]], [[V1]]167; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>168; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i32> [[V0]], [[V1]]169; CHECK-NEXT: [[TMP9:%.*]] = add <2 x i32> [[TMP7]], [[TMP8]]170; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>171; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>172; CHECK-NEXT: [[TMP3_31:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>173; CHECK-NEXT: ret <4 x i32> [[TMP3_31]]174;175 %v0.0 = extractelement <2 x i32> %v0, i32 0176 %v0.1 = extractelement <2 x i32> %v0, i32 1177 %v1.0 = extractelement <2 x i32> %v1, i32 0178 %v1.1 = extractelement <2 x i32> %v1, i32 1179 %tmp0.0 = add i32 %v0.0, %v1.0180 %tmp0.1 = add i32 %v0.1, %v1.1181 %tmp0.2 = xor i32 %v0.0, %v1.0182 %tmp0.3 = xor i32 %v0.1, %v1.1183 %tmp1.0 = mul i32 %v0.0, %v1.0184 %tmp1.1 = mul i32 %v0.1, %v1.1185 %tmp1.2 = xor i32 %v0.0, %v1.0186 %tmp1.3 = xor i32 %v0.1, %v1.1187 %tmp2.0 = add i32 %tmp0.0, %tmp0.1188 %tmp2.1 = add i32 %tmp1.0, %tmp1.1189 %tmp2.2 = add i32 %tmp0.2, %tmp0.3190 %tmp2.3 = add i32 %tmp1.2, %tmp1.3191 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0192 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1193 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2194 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3195 ret <4 x i32> %tmp3.3196}197 198define i32 @reduction_v4i32(<4 x i32> %v0, <4 x i32> %v1) {199; CHECK-LABEL: @reduction_v4i32(200; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> [[V0:%.*]], [[V1:%.*]]201; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[V0]], [[V1]]202; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>203; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>204; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP4]], [[TMP3]]205; CHECK-NEXT: [[TMP6:%.*]] = lshr <4 x i32> [[TMP5]], splat (i32 15)206; CHECK-NEXT: [[TMP7:%.*]] = and <4 x i32> [[TMP6]], splat (i32 65537)207; CHECK-NEXT: [[TMP8:%.*]] = mul nuw <4 x i32> [[TMP7]], splat (i32 65535)208; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP5]]209; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i32> [[TMP9]], [[TMP8]]210; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP10]])211; CHECK-NEXT: ret i32 [[TMP11]]212;213 %v0.0 = extractelement <4 x i32> %v0, i32 0214 %v0.1 = extractelement <4 x i32> %v0, i32 1215 %v0.2 = extractelement <4 x i32> %v0, i32 2216 %v0.3 = extractelement <4 x i32> %v0, i32 3217 %v1.0 = extractelement <4 x i32> %v1, i32 0218 %v1.1 = extractelement <4 x i32> %v1, i32 1219 %v1.2 = extractelement <4 x i32> %v1, i32 2220 %v1.3 = extractelement <4 x i32> %v1, i32 3221 %tmp0.0 = add i32 %v0.0, %v1.0222 %tmp0.1 = add i32 %v0.1, %v1.1223 %tmp0.2 = add i32 %v0.2, %v1.2224 %tmp0.3 = add i32 %v0.3, %v1.3225 %tmp1.0 = sub i32 %v0.0, %v1.0226 %tmp1.1 = sub i32 %v0.1, %v1.1227 %tmp1.2 = sub i32 %v0.2, %v1.2228 %tmp1.3 = sub i32 %v0.3, %v1.3229 %tmp2.0 = add i32 %tmp0.0, %tmp0.1230 %tmp2.1 = add i32 %tmp1.0, %tmp1.1231 %tmp2.2 = add i32 %tmp0.2, %tmp0.3232 %tmp2.3 = add i32 %tmp1.2, %tmp1.3233 %tmp3.0 = lshr i32 %tmp2.0, 15234 %tmp3.1 = lshr i32 %tmp2.1, 15235 %tmp3.2 = lshr i32 %tmp2.2, 15236 %tmp3.3 = lshr i32 %tmp2.3, 15237 %tmp4.0 = and i32 %tmp3.0, 65537238 %tmp4.1 = and i32 %tmp3.1, 65537239 %tmp4.2 = and i32 %tmp3.2, 65537240 %tmp4.3 = and i32 %tmp3.3, 65537241 %tmp5.0 = mul nuw i32 %tmp4.0, 65535242 %tmp5.1 = mul nuw i32 %tmp4.1, 65535243 %tmp5.2 = mul nuw i32 %tmp4.2, 65535244 %tmp5.3 = mul nuw i32 %tmp4.3, 65535245 %tmp6.0 = add i32 %tmp5.0, %tmp2.0246 %tmp6.1 = add i32 %tmp5.1, %tmp2.1247 %tmp6.2 = add i32 %tmp5.2, %tmp2.2248 %tmp6.3 = add i32 %tmp5.3, %tmp2.3249 %tmp7.0 = xor i32 %tmp6.0, %tmp5.0250 %tmp7.1 = xor i32 %tmp6.1, %tmp5.1251 %tmp7.2 = xor i32 %tmp6.2, %tmp5.2252 %tmp7.3 = xor i32 %tmp6.3, %tmp5.3253 %reduce.0 = add i32 %tmp7.1, %tmp7.0254 %reduce.1 = add i32 %reduce.0, %tmp7.2255 %reduce.2 = add i32 %reduce.1, %tmp7.3256 ret i32 %reduce.2257}258