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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-unknown | FileCheck %s3 4; This test is reduced from the TSVC evaluation of vectorizers:5; https://github.com/llvm/llvm-test-suite/commits/main/MultiSource/Benchmarks/TSVC/LoopRerolling-flt/tsc.c6 7; FIXME8; This test is currently getting vectorized with VF=2. We should be able9; to vectorize it with VF=4. Specifically, we should be able to have 1 load of10; <4 x float> instead of 2 loads of <2 x float>, and there should be no need11; for shufflevectors.12; The current issue comes from the Left-Hand-Side fmul operands.13; These operands are coming from 4 loads which are not14; contiguous. The score estimation needs to be corrected, so that these 4 loads15; are not selected for vectorization. Instead we should vectorize with16; contiguous loads, from %a plus offsets 0 to 3, or offsets 1 to 4.17 18define void @s116_modified(ptr %a) {19; CHECK-LABEL: @s116_modified(20; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds float, ptr [[GEP1:%.*]], i64 421; CHECK-NEXT: [[LD0:%.*]] = load float, ptr [[A]], align 422; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[GEP1]], align 423; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 0, i32 2, i32 3, i32 poison>24; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP2]], float [[LD0]], i32 325; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 2, i32 3>26; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <4 x float> [[TMP6]], [[TMP7]]27; CHECK-NEXT: store <4 x float> [[TMP8]], ptr [[GEP1]], align 428; CHECK-NEXT: ret void29;30 %gep1 = getelementptr inbounds float, ptr %a, i64 131 %gep2 = getelementptr inbounds float, ptr %a, i64 232 %gep3 = getelementptr inbounds float, ptr %a, i64 333 %gep4 = getelementptr inbounds float, ptr %a, i64 434 %ld0 = load float, ptr %a35 %ld1 = load float, ptr %gep136 %ld2 = load float, ptr %gep237 %ld3 = load float, ptr %gep338 %ld4 = load float, ptr %gep439 %mul0 = fmul fast float %ld0, %ld140 %mul1 = fmul fast float %ld2, %ld141 %mul2 = fmul fast float %ld3, %ld242 %mul3 = fmul fast float %ld4, %ld343 store float %mul0, ptr %a44 store float %mul1, ptr %gep145 store float %mul2, ptr %gep246 store float %mul3, ptr %gep347 ret void48}49 50 51