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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define void @h() {5; CHECK-LABEL: define void @h() {6; CHECK-NEXT: entry:7; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 168; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 29; CHECK-NEXT: ret void10;11entry:12 %arrayidx2 = getelementptr i8, ptr null, i64 1613 %conv310 = zext i16 0 to i3214 %add4 = or i32 %conv310, 015 %sub = or i32 0, %conv31016 %conv15 = sext i16 0 to i3217 %shr = ashr i32 %conv15, 018 %arrayidx18 = getelementptr i8, ptr null, i64 2419 %conv19 = sext i16 0 to i3220 %sub20 = or i32 %shr, 021 %shr29 = ashr i32 %conv19, 022 %add30 = or i32 %shr29, %conv1523 %sub39 = or i32 %sub, %sub2024 %conv40 = trunc i32 %sub39 to i1625 store i16 %conv40, ptr %arrayidx2, align 226 %sub44 = or i32 %add4, %add3027 %conv45 = trunc i32 %sub44 to i1628 store i16 %conv45, ptr %arrayidx18, align 229 %arrayidx2.1 = getelementptr i8, ptr null, i64 1830 %conv3.112 = zext i16 0 to i3231 %add4.1 = or i32 %conv3.112, 032 %sub.1 = or i32 0, %conv3.11233 %conv15.1 = sext i16 0 to i3234 %shr.1 = ashr i32 %conv15.1, 035 %arrayidx18.1 = getelementptr i8, ptr null, i64 2636 %conv19.1 = sext i16 0 to i3237 %sub20.1 = or i32 %shr.1, 038 %shr29.1 = ashr i32 %conv19.1, 039 %add30.1 = or i32 %shr29.1, 040 %sub39.1 = or i32 %sub.1, %sub20.141 %conv40.1 = trunc i32 %sub39.1 to i1642 store i16 %conv40.1, ptr %arrayidx2.1, align 243 %sub44.1 = or i32 %add4.1, %add30.144 %conv45.1 = trunc i32 %sub44.1 to i1645 store i16 %conv45.1, ptr %arrayidx18.1, align 246 %conv.213 = zext i16 0 to i3247 %arrayidx2.2 = getelementptr i8, ptr null, i64 2048 %conv3.214 = zext i16 0 to i3249 %add4.2 = or i32 0, %conv.21350 %sub.2 = or i32 0, %conv3.21451 %conv15.2 = sext i16 0 to i3252 %shr.2 = ashr i32 %conv15.2, 053 %arrayidx18.2 = getelementptr i8, ptr null, i64 2854 %conv19.2 = sext i16 0 to i3255 %sub20.2 = or i32 %shr.2, 056 %shr29.2 = ashr i32 %conv19.2, 057 %add30.2 = or i32 %shr29.2, 058 %sub39.2 = or i32 %sub.2, %sub20.259 %conv40.2 = trunc i32 %sub39.2 to i1660 store i16 %conv40.2, ptr %arrayidx2.2, align 261 %sub44.2 = or i32 %add4.2, %add30.262 %conv45.2 = trunc i32 %sub44.2 to i1663 store i16 %conv45.2, ptr %arrayidx18.2, align 264 %conv.315 = zext i16 0 to i3265 %arrayidx2.3 = getelementptr i8, ptr null, i64 2266 %conv3.316 = zext i16 0 to i3267 %add4.3 = or i32 0, %conv.31568 %sub.3 = or i32 0, %conv3.31669 %conv15.3 = sext i16 0 to i3270 %shr.3 = ashr i32 %conv15.3, 071 %arrayidx18.3 = getelementptr i8, ptr null, i64 3072 %conv19.3 = sext i16 0 to i3273 %sub20.3 = or i32 %shr.3, 074 %shr29.3 = ashr i32 %conv19.3, 075 %add30.3 = or i32 %shr29.3, 076 %sub39.3 = or i32 %sub.3, %sub20.377 %conv40.3 = trunc i32 %sub39.3 to i1678 store i16 %conv40.3, ptr %arrayidx2.3, align 279 %sub44.3 = or i32 %add4.3, %add30.380 %conv45.3 = trunc i32 %sub44.3 to i1681 store i16 %conv45.3, ptr %arrayidx18.3, align 282 ret void83}84