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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -mtriple=arm64-apple-ios -S %s | FileCheck --check-prefixes=CHECK,NON-POW2 %s3; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -mtriple=arm64-apple-ios -S %s | FileCheck --check-prefixes=CHECK,POW2-ONLY %s4 5define void @v3_load_i32_mul_by_constant_store(ptr %src, ptr %dst) {6; NON-POW2-LABEL: @v3_load_i32_mul_by_constant_store(7; NON-POW2-NEXT: entry:8; NON-POW2-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 09; NON-POW2-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr [[GEP_SRC_0]], align 410; NON-POW2-NEXT: [[TMP1:%.*]] = mul nsw <3 x i32> [[TMP0]], splat (i32 10)11; NON-POW2-NEXT: store <3 x i32> [[TMP1]], ptr [[DST:%.*]], align 412; NON-POW2-NEXT: ret void13;14; POW2-ONLY-LABEL: @v3_load_i32_mul_by_constant_store(15; POW2-ONLY-NEXT: entry:16; POW2-ONLY-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 017; POW2-ONLY-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 218; POW2-ONLY-NEXT: [[L_SRC_2:%.*]] = load i32, ptr [[GEP_SRC_2]], align 419; POW2-ONLY-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_2]], 1020; POW2-ONLY-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[GEP_SRC_0]], align 421; POW2-ONLY-NEXT: [[TMP1:%.*]] = mul nsw <2 x i32> [[TMP0]], splat (i32 10)22; POW2-ONLY-NEXT: store <2 x i32> [[TMP1]], ptr [[DST:%.*]], align 423; POW2-ONLY-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 224; POW2-ONLY-NEXT: store i32 [[MUL_2]], ptr [[DST_2]], align 425; POW2-ONLY-NEXT: ret void26;27entry:28 %gep.src.0 = getelementptr inbounds i32, ptr %src, i32 029 %l.src.0 = load i32, ptr %gep.src.0, align 430 %mul.0 = mul nsw i32 %l.src.0, 1031 32 %gep.src.1 = getelementptr inbounds i32, ptr %src, i32 133 %l.src.1 = load i32, ptr %gep.src.1, align 434 %mul.1 = mul nsw i32 %l.src.1, 1035 36 %gep.src.2 = getelementptr inbounds i32, ptr %src, i32 237 %l.src.2 = load i32, ptr %gep.src.2, align 438 %mul.2 = mul nsw i32 %l.src.2, 1039 40 store i32 %mul.0, ptr %dst41 42 %dst.1 = getelementptr i32, ptr %dst, i32 143 store i32 %mul.1, ptr %dst.144 45 %dst.2 = getelementptr i32, ptr %dst, i32 246 store i32 %mul.2, ptr %dst.247 48 ret void49}50 51; Should no be vectorized with a undef/poison element as padding, as division by undef/poison may cause UB.52define void @v3_load_i32_udiv_by_constant_store(ptr %src, ptr %dst) {53; CHECK-LABEL: @v3_load_i32_udiv_by_constant_store(54; CHECK-NEXT: entry:55; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 056; CHECK-NEXT: [[L_SRC_0:%.*]] = load i32, ptr [[GEP_SRC_0]], align 457; CHECK-NEXT: [[MUL_0:%.*]] = udiv i32 10, [[L_SRC_0]]58; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 159; CHECK-NEXT: [[L_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 460; CHECK-NEXT: [[MUL_1:%.*]] = udiv i32 10, [[L_SRC_1]]61; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 262; CHECK-NEXT: [[L_SRC_2:%.*]] = load i32, ptr [[GEP_SRC_2]], align 463; CHECK-NEXT: [[MUL_2:%.*]] = udiv i32 10, [[L_SRC_2]]64; CHECK-NEXT: store i32 [[MUL_0]], ptr [[DST:%.*]], align 465; CHECK-NEXT: [[DST_1:%.*]] = getelementptr i32, ptr [[DST]], i32 166; CHECK-NEXT: store i32 [[MUL_1]], ptr [[DST_1]], align 467; CHECK-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 268; CHECK-NEXT: store i32 [[MUL_2]], ptr [[DST_2]], align 469; CHECK-NEXT: ret void70;71entry:72 %gep.src.0 = getelementptr inbounds i32, ptr %src, i32 073 %l.src.0 = load i32, ptr %gep.src.0, align 474 %mul.0 = udiv i32 10, %l.src.075 76 %gep.src.1 = getelementptr inbounds i32, ptr %src, i32 177 %l.src.1 = load i32, ptr %gep.src.1, align 478 %mul.1 = udiv i32 10, %l.src.179 80 %gep.src.2 = getelementptr inbounds i32, ptr %src, i32 281 %l.src.2 = load i32, ptr %gep.src.2, align 482 %mul.2 = udiv i32 10, %l.src.283 84 store i32 %mul.0, ptr %dst85 86 %dst.1 = getelementptr i32, ptr %dst, i32 187 store i32 %mul.1, ptr %dst.188 89 %dst.2 = getelementptr i32, ptr %dst, i32 290 store i32 %mul.2, ptr %dst.291 92 ret void93}94 95 96 97define void @v3_load_i32_mul_store(ptr %src.1, ptr %src.2, ptr %dst) {98; NON-POW2-LABEL: @v3_load_i32_mul_store(99; NON-POW2-NEXT: entry:100; NON-POW2-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0101; NON-POW2-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0102; NON-POW2-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr [[GEP_SRC_1_0]], align 4103; NON-POW2-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[GEP_SRC_2_0]], align 4104; NON-POW2-NEXT: [[TMP2:%.*]] = mul nsw <3 x i32> [[TMP0]], [[TMP1]]105; NON-POW2-NEXT: store <3 x i32> [[TMP2]], ptr [[DST:%.*]], align 4106; NON-POW2-NEXT: ret void107;108; POW2-ONLY-LABEL: @v3_load_i32_mul_store(109; POW2-ONLY-NEXT: entry:110; POW2-ONLY-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0111; POW2-ONLY-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0112; POW2-ONLY-NEXT: [[GEP_SRC_1_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 2113; POW2-ONLY-NEXT: [[L_SRC_1_2:%.*]] = load i32, ptr [[GEP_SRC_1_2]], align 4114; POW2-ONLY-NEXT: [[GEP_SRC_2_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 2115; POW2-ONLY-NEXT: [[L_SRC_2_2:%.*]] = load i32, ptr [[GEP_SRC_2_2]], align 4116; POW2-ONLY-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_1_2]], [[L_SRC_2_2]]117; POW2-ONLY-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[GEP_SRC_1_0]], align 4118; POW2-ONLY-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[GEP_SRC_2_0]], align 4119; POW2-ONLY-NEXT: [[TMP2:%.*]] = mul nsw <2 x i32> [[TMP0]], [[TMP1]]120; POW2-ONLY-NEXT: store <2 x i32> [[TMP2]], ptr [[DST:%.*]], align 4121; POW2-ONLY-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 2122; POW2-ONLY-NEXT: store i32 [[MUL_2]], ptr [[DST_2]], align 4123; POW2-ONLY-NEXT: ret void124;125entry:126 %gep.src.1.0 = getelementptr inbounds i32, ptr %src.1, i32 0127 %l.src.1.0 = load i32, ptr %gep.src.1.0, align 4128 %gep.src.2.0 = getelementptr inbounds i32, ptr %src.2, i32 0129 %l.src.2.0 = load i32, ptr %gep.src.2.0, align 4130 %mul.0 = mul nsw i32 %l.src.1.0, %l.src.2.0131 132 %gep.src.1.1 = getelementptr inbounds i32, ptr %src.1, i32 1133 %l.src.1.1 = load i32, ptr %gep.src.1.1, align 4134 %gep.src.2.1 = getelementptr inbounds i32, ptr %src.2, i32 1135 %l.src.2.1 = load i32, ptr %gep.src.2.1, align 4136 %mul.1 = mul nsw i32 %l.src.1.1, %l.src.2.1137 138 %gep.src.1.2 = getelementptr inbounds i32, ptr %src.1, i32 2139 %l.src.1.2 = load i32, ptr %gep.src.1.2, align 4140 %gep.src.2.2 = getelementptr inbounds i32, ptr %src.2, i32 2141 %l.src.2.2 = load i32, ptr %gep.src.2.2, align 4142 %mul.2 = mul nsw i32 %l.src.1.2, %l.src.2.2143 144 store i32 %mul.0, ptr %dst145 146 %dst.1 = getelementptr i32, ptr %dst, i32 1147 store i32 %mul.1, ptr %dst.1148 149 %dst.2 = getelementptr i32, ptr %dst, i32 2150 store i32 %mul.2, ptr %dst.2151 152 ret void153}154 155define void @v3_load_i32_mul_add_const_store(ptr %src.1, ptr %src.2, ptr %dst) {156; NON-POW2-LABEL: @v3_load_i32_mul_add_const_store(157; NON-POW2-NEXT: entry:158; NON-POW2-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0159; NON-POW2-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0160; NON-POW2-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr [[GEP_SRC_1_0]], align 4161; NON-POW2-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[GEP_SRC_2_0]], align 4162; NON-POW2-NEXT: [[TMP2:%.*]] = mul nsw <3 x i32> [[TMP0]], [[TMP1]]163; NON-POW2-NEXT: [[TMP3:%.*]] = add <3 x i32> [[TMP2]], splat (i32 9)164; NON-POW2-NEXT: store <3 x i32> [[TMP3]], ptr [[DST:%.*]], align 4165; NON-POW2-NEXT: ret void166;167; POW2-ONLY-LABEL: @v3_load_i32_mul_add_const_store(168; POW2-ONLY-NEXT: entry:169; POW2-ONLY-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0170; POW2-ONLY-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0171; POW2-ONLY-NEXT: [[GEP_SRC_1_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 2172; POW2-ONLY-NEXT: [[L_SRC_1_2:%.*]] = load i32, ptr [[GEP_SRC_1_2]], align 4173; POW2-ONLY-NEXT: [[GEP_SRC_2_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 2174; POW2-ONLY-NEXT: [[L_SRC_2_2:%.*]] = load i32, ptr [[GEP_SRC_2_2]], align 4175; POW2-ONLY-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_1_2]], [[L_SRC_2_2]]176; POW2-ONLY-NEXT: [[ADD_2:%.*]] = add i32 [[MUL_2]], 9177; POW2-ONLY-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[GEP_SRC_1_0]], align 4178; POW2-ONLY-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[GEP_SRC_2_0]], align 4179; POW2-ONLY-NEXT: [[TMP2:%.*]] = mul nsw <2 x i32> [[TMP0]], [[TMP1]]180; POW2-ONLY-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], splat (i32 9)181; POW2-ONLY-NEXT: store <2 x i32> [[TMP3]], ptr [[DST:%.*]], align 4182; POW2-ONLY-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 2183; POW2-ONLY-NEXT: store i32 [[ADD_2]], ptr [[DST_2]], align 4184; POW2-ONLY-NEXT: ret void185;186entry:187 %gep.src.1.0 = getelementptr inbounds i32, ptr %src.1, i32 0188 %l.src.1.0 = load i32, ptr %gep.src.1.0, align 4189 %gep.src.2.0 = getelementptr inbounds i32, ptr %src.2, i32 0190 %l.src.2.0 = load i32, ptr %gep.src.2.0, align 4191 %mul.0 = mul nsw i32 %l.src.1.0, %l.src.2.0192 %add.0 = add i32 %mul.0, 9193 194 %gep.src.1.1 = getelementptr inbounds i32, ptr %src.1, i32 1195 %l.src.1.1 = load i32, ptr %gep.src.1.1, align 4196 %gep.src.2.1 = getelementptr inbounds i32, ptr %src.2, i32 1197 %l.src.2.1 = load i32, ptr %gep.src.2.1, align 4198 %mul.1 = mul nsw i32 %l.src.1.1, %l.src.2.1199 %add.1 = add i32 %mul.1, 9200 201 %gep.src.1.2 = getelementptr inbounds i32, ptr %src.1, i32 2202 %l.src.1.2 = load i32, ptr %gep.src.1.2, align 4203 %gep.src.2.2 = getelementptr inbounds i32, ptr %src.2, i32 2204 %l.src.2.2 = load i32, ptr %gep.src.2.2, align 4205 %mul.2 = mul nsw i32 %l.src.1.2, %l.src.2.2206 %add.2 = add i32 %mul.2, 9207 208 store i32 %add.0, ptr %dst209 210 %dst.1 = getelementptr i32, ptr %dst, i32 1211 store i32 %add.1, ptr %dst.1212 213 %dst.2 = getelementptr i32, ptr %dst, i32 2214 store i32 %add.2, ptr %dst.2215 216 ret void217}218 219define void @v3_load_f32_fadd_fadd_by_constant_store(ptr %src, ptr %dst) {220; NON-POW2-LABEL: @v3_load_f32_fadd_fadd_by_constant_store(221; NON-POW2-NEXT: entry:222; NON-POW2-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds float, ptr [[SRC:%.*]], i32 0223; NON-POW2-NEXT: [[TMP0:%.*]] = load <3 x float>, ptr [[GEP_SRC_0]], align 4224; NON-POW2-NEXT: [[TMP1:%.*]] = fadd <3 x float> [[TMP0]], splat (float 1.000000e+01)225; NON-POW2-NEXT: store <3 x float> [[TMP1]], ptr [[DST:%.*]], align 4226; NON-POW2-NEXT: ret void227;228; POW2-ONLY-LABEL: @v3_load_f32_fadd_fadd_by_constant_store(229; POW2-ONLY-NEXT: entry:230; POW2-ONLY-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds float, ptr [[SRC:%.*]], i32 0231; POW2-ONLY-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds float, ptr [[SRC]], i32 2232; POW2-ONLY-NEXT: [[L_SRC_2:%.*]] = load float, ptr [[GEP_SRC_2]], align 4233; POW2-ONLY-NEXT: [[FADD_2:%.*]] = fadd float [[L_SRC_2]], 1.000000e+01234; POW2-ONLY-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[GEP_SRC_0]], align 4235; POW2-ONLY-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[TMP0]], splat (float 1.000000e+01)236; POW2-ONLY-NEXT: store <2 x float> [[TMP1]], ptr [[DST:%.*]], align 4237; POW2-ONLY-NEXT: [[DST_2:%.*]] = getelementptr float, ptr [[DST]], i32 2238; POW2-ONLY-NEXT: store float [[FADD_2]], ptr [[DST_2]], align 4239; POW2-ONLY-NEXT: ret void240;241entry:242 %gep.src.0 = getelementptr inbounds float, ptr %src, i32 0243 %l.src.0 = load float , ptr %gep.src.0, align 4244 %fadd.0 = fadd float %l.src.0, 10.0245 246 %gep.src.1 = getelementptr inbounds float , ptr %src, i32 1247 %l.src.1 = load float, ptr %gep.src.1, align 4248 %fadd.1 = fadd float %l.src.1, 10.0249 250 %gep.src.2 = getelementptr inbounds float, ptr %src, i32 2251 %l.src.2 = load float, ptr %gep.src.2, align 4252 %fadd.2 = fadd float %l.src.2, 10.0253 254 store float %fadd.0, ptr %dst255 256 %dst.1 = getelementptr float, ptr %dst, i32 1257 store float %fadd.1, ptr %dst.1258 259 %dst.2 = getelementptr float, ptr %dst, i32 2260 store float %fadd.2, ptr %dst.2261 262 ret void263}264 265define void @phi_store3(ptr %dst) {266; NON-POW2-LABEL: @phi_store3(267; NON-POW2-NEXT: entry:268; NON-POW2-NEXT: br label [[EXIT:%.*]]269; NON-POW2: invoke.cont8.loopexit:270; NON-POW2-NEXT: br label [[EXIT]]271; NON-POW2: exit:272; NON-POW2-NEXT: [[TMP0:%.*]] = phi <3 x i32> [ <i32 1, i32 2, i32 3>, [[ENTRY:%.*]] ], [ poison, [[INVOKE_CONT8_LOOPEXIT:%.*]] ]273; NON-POW2-NEXT: store <3 x i32> [[TMP0]], ptr [[DST:%.*]], align 4274; NON-POW2-NEXT: ret void275;276; POW2-ONLY-LABEL: @phi_store3(277; POW2-ONLY-NEXT: entry:278; POW2-ONLY-NEXT: br label [[EXIT:%.*]]279; POW2-ONLY: invoke.cont8.loopexit:280; POW2-ONLY-NEXT: br label [[EXIT]]281; POW2-ONLY: exit:282; POW2-ONLY-NEXT: [[P_2:%.*]] = phi i32 [ 3, [[ENTRY:%.*]] ], [ 0, [[INVOKE_CONT8_LOOPEXIT:%.*]] ]283; POW2-ONLY-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ <i32 1, i32 2>, [[ENTRY]] ], [ poison, [[INVOKE_CONT8_LOOPEXIT]] ]284; POW2-ONLY-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST:%.*]], i32 2285; POW2-ONLY-NEXT: store <2 x i32> [[TMP0]], ptr [[DST]], align 4286; POW2-ONLY-NEXT: store i32 [[P_2]], ptr [[DST_2]], align 4287; POW2-ONLY-NEXT: ret void288;289entry:290 br label %exit291 292invoke.cont8.loopexit: ; No predecessors!293 br label %exit294 295exit:296 %p.0 = phi i32 [ 1, %entry ], [ 0, %invoke.cont8.loopexit ]297 %p.1 = phi i32 [ 2, %entry ], [ 0, %invoke.cont8.loopexit ]298 %p.2 = phi i32 [ 3, %entry ], [ 0, %invoke.cont8.loopexit ]299 300 %dst.1 = getelementptr i32, ptr %dst, i32 1301 %dst.2 = getelementptr i32, ptr %dst, i32 2302 303 store i32 %p.0, ptr %dst, align 4304 store i32 %p.1, ptr %dst.1, align 4305 store i32 %p.2, ptr %dst.2, align 4306 ret void307}308 309define void @store_try_reorder(ptr %dst) {310; NON-POW2-LABEL: @store_try_reorder(311; NON-POW2-NEXT: entry:312; NON-POW2-NEXT: store <3 x i32> zeroinitializer, ptr [[DST:%.*]], align 4313; NON-POW2-NEXT: ret void314;315; POW2-ONLY-LABEL: @store_try_reorder(316; POW2-ONLY-NEXT: entry:317; POW2-ONLY-NEXT: store <2 x i32> zeroinitializer, ptr [[ARRAYIDX_I1887:%.*]], align 4318; POW2-ONLY-NEXT: [[ADD216:%.*]] = sub i32 0, 0319; POW2-ONLY-NEXT: [[ARRAYIDX_I1891:%.*]] = getelementptr i32, ptr [[ARRAYIDX_I1887]], i64 2320; POW2-ONLY-NEXT: store i32 [[ADD216]], ptr [[ARRAYIDX_I1891]], align 4321; POW2-ONLY-NEXT: ret void322;323entry:324 %add = add i32 0, 0325 store i32 %add, ptr %dst, align 4326 %add207 = sub i32 0, 0327 %arrayidx.i1887 = getelementptr i32, ptr %dst, i64 1328 store i32 %add207, ptr %arrayidx.i1887, align 4329 %add216 = sub i32 0, 0330 %arrayidx.i1891 = getelementptr i32, ptr %dst, i64 2331 store i32 %add216, ptr %arrayidx.i1891, align 4332 ret void333}334 335define void @vec3_fpext_cost(ptr %Colour, float %0) {336; CHECK-LABEL: @vec3_fpext_cost(337; CHECK-NEXT: entry:338; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2339; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i32 0340; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer341; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>342; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP3]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)343; CHECK-NEXT: [[TMP5:%.*]] = fptrunc <2 x double> [[TMP4]] to <2 x float>344; CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[COLOUR]], align 4345; CHECK-NEXT: [[CONV78:%.*]] = fpext float [[TMP0]] to double346; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.fmuladd.f64(double [[CONV78]], double 0.000000e+00, double 0.000000e+00)347; CHECK-NEXT: [[CONV82:%.*]] = fptrunc double [[TMP6]] to float348; CHECK-NEXT: store float [[CONV82]], ptr [[ARRAYIDX80]], align 4349; CHECK-NEXT: ret void350;351entry:352 %arrayidx72 = getelementptr float, ptr %Colour, i64 1353 %arrayidx80 = getelementptr float, ptr %Colour, i64 2354 %conv62 = fpext float %0 to double355 %1 = call double @llvm.fmuladd.f64(double %conv62, double 0.000000e+00, double 0.000000e+00)356 %conv66 = fptrunc double %1 to float357 store float %conv66, ptr %Colour, align 4358 %conv70 = fpext float %0 to double359 %2 = call double @llvm.fmuladd.f64(double %conv70, double 0.000000e+00, double 0.000000e+00)360 %conv74 = fptrunc double %2 to float361 store float %conv74, ptr %arrayidx72, align 4362 %conv78 = fpext float %0 to double363 %3 = call double @llvm.fmuladd.f64(double %conv78, double 0.000000e+00, double 0.000000e+00)364 %conv82 = fptrunc double %3 to float365 store float %conv82, ptr %arrayidx80, align 4366 ret void367}368 369define void @fpext_gather(ptr %dst, double %conv) {370; CHECK-LABEL: @fpext_gather(371; CHECK-NEXT: entry:372; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV:%.*]], i32 0373; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer374; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>375; CHECK-NEXT: [[LENGTHS:%.*]] = getelementptr float, ptr [[DST:%.*]], i64 0376; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0377; CHECK-NEXT: store float [[TMP3]], ptr [[LENGTHS]], align 4378; CHECK-NEXT: [[ARRAYIDX32:%.*]] = getelementptr float, ptr [[DST]], i64 1379; CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[ARRAYIDX32]], align 4380; CHECK-NEXT: ret void381;382entry:383 %conv25 = fptrunc double %conv to float384 %Lengths = getelementptr float, ptr %dst, i64 0385 store float %conv25, ptr %Lengths, align 4386 %arrayidx32 = getelementptr float, ptr %dst, i64 1387 store float %conv25, ptr %arrayidx32, align 4388 %conv34 = fptrunc double %conv to float389 %arrayidx37 = getelementptr float, ptr %dst, i64 2390 store float %conv34, ptr %arrayidx37, align 4391 ret void392}393 394declare float @llvm.fmuladd.f32(float, float, float)395 396declare double @llvm.fmuladd.f64(double, double, double)397