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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s4 5; FIXME: Should still like to vectorize the memory operations for VI6 7; Simple 3-pair chain with loads and stores8define amdgpu_kernel void @test1_as_3_3_3_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %b, ptr addrspace(3) %c) {9; GCN-LABEL: @test1_as_3_3_3_v2f16(10; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 211; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(3) [[B:%.*]], align 212; GCN-NEXT: [[TMP3:%.*]] = fmul <2 x half> [[TMP1]], [[TMP2]]13; GCN-NEXT: store <2 x half> [[TMP3]], ptr addrspace(3) [[C:%.*]], align 214; GCN-NEXT: ret void15;16 %i0 = load half, ptr addrspace(3) %a, align 217 %i1 = load half, ptr addrspace(3) %b, align 218 %mul = fmul half %i0, %i119 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 120 %i3 = load half, ptr addrspace(3) %arrayidx3, align 221 %arrayidx4 = getelementptr inbounds half, ptr addrspace(3) %b, i64 122 %i4 = load half, ptr addrspace(3) %arrayidx4, align 223 %mul5 = fmul half %i3, %i424 store half %mul, ptr addrspace(3) %c, align 225 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 126 store half %mul5, ptr addrspace(3) %arrayidx5, align 227 ret void28}29 30define amdgpu_kernel void @test1_as_3_0_0(ptr addrspace(3) %a, ptr %b, ptr %c) {31; GCN-LABEL: @test1_as_3_0_0(32; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 233; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[B:%.*]], align 234; GCN-NEXT: [[TMP3:%.*]] = fmul <2 x half> [[TMP1]], [[TMP2]]35; GCN-NEXT: store <2 x half> [[TMP3]], ptr [[C:%.*]], align 236; GCN-NEXT: ret void37;38 %i0 = load half, ptr addrspace(3) %a, align 239 %i1 = load half, ptr %b, align 240 %mul = fmul half %i0, %i141 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 142 %i3 = load half, ptr addrspace(3) %arrayidx3, align 243 %arrayidx4 = getelementptr inbounds half, ptr %b, i64 144 %i4 = load half, ptr %arrayidx4, align 245 %mul5 = fmul half %i3, %i446 store half %mul, ptr %c, align 247 %arrayidx5 = getelementptr inbounds half, ptr %c, i64 148 store half %mul5, ptr %arrayidx5, align 249 ret void50}51 52define amdgpu_kernel void @test1_as_0_0_3_v2f16(ptr %a, ptr %b, ptr addrspace(3) %c) {53; GCN-LABEL: @test1_as_0_0_3_v2f16(54; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[A:%.*]], align 255; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[B:%.*]], align 256; GCN-NEXT: [[TMP3:%.*]] = fmul <2 x half> [[TMP1]], [[TMP2]]57; GCN-NEXT: store <2 x half> [[TMP3]], ptr addrspace(3) [[C:%.*]], align 258; GCN-NEXT: ret void59;60 %i0 = load half, ptr %a, align 261 %i1 = load half, ptr %b, align 262 %mul = fmul half %i0, %i163 %arrayidx3 = getelementptr inbounds half, ptr %a, i64 164 %i3 = load half, ptr %arrayidx3, align 265 %arrayidx4 = getelementptr inbounds half, ptr %b, i64 166 %i4 = load half, ptr %arrayidx4, align 267 %mul5 = fmul half %i3, %i468 store half %mul, ptr addrspace(3) %c, align 269 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 170 store half %mul5, ptr addrspace(3) %arrayidx5, align 271 ret void72}73 74define amdgpu_kernel void @test1_fma_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %b, ptr addrspace(3) %c, ptr addrspace(3) %d) {75; GCN-LABEL: @test1_fma_v2f16(76; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 277; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(3) [[B:%.*]], align 278; GCN-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(3) [[C:%.*]], align 279; GCN-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP1]], <2 x half> [[TMP2]], <2 x half> [[TMP3]])80; GCN-NEXT: store <2 x half> [[TMP4]], ptr addrspace(3) [[D:%.*]], align 281; GCN-NEXT: ret void82;83 %i0 = load half, ptr addrspace(3) %a, align 284 %i1 = load half, ptr addrspace(3) %b, align 285 %i2 = load half, ptr addrspace(3) %c, align 286 %fma0 = call half @llvm.fma.f16(half %i0, half %i1, half %i2)87 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 188 %i3 = load half, ptr addrspace(3) %arrayidx3, align 289 %arrayidx4 = getelementptr inbounds half, ptr addrspace(3) %b, i64 190 %i4 = load half, ptr addrspace(3) %arrayidx4, align 291 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 192 %i5 = load half, ptr addrspace(3) %arrayidx5, align 293 %fma1 = call half @llvm.fma.f16(half %i3, half %i4, half %i5)94 store half %fma0, ptr addrspace(3) %d, align 295 %arrayidx6 = getelementptr inbounds half, ptr addrspace(3) %d, i64 196 store half %fma1, ptr addrspace(3) %arrayidx6, align 297 ret void98}99 100define amdgpu_kernel void @mul_scalar_v2f16(ptr addrspace(3) %a, half %scalar, ptr addrspace(3) %c) {101; GCN-LABEL: @mul_scalar_v2f16(102; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2103; GCN-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[SCALAR:%.*]], i32 0104; GCN-NEXT: [[TMP3:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <2 x i32> zeroinitializer105; GCN-NEXT: [[TMP4:%.*]] = fmul <2 x half> [[TMP1]], [[TMP3]]106; GCN-NEXT: store <2 x half> [[TMP4]], ptr addrspace(3) [[C:%.*]], align 2107; GCN-NEXT: ret void108;109 %i0 = load half, ptr addrspace(3) %a, align 2110 %mul = fmul half %i0, %scalar111 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 1112 %i3 = load half, ptr addrspace(3) %arrayidx3, align 2113 %mul5 = fmul half %i3, %scalar114 store half %mul, ptr addrspace(3) %c, align 2115 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 1116 store half %mul5, ptr addrspace(3) %arrayidx5, align 2117 ret void118}119 120define amdgpu_kernel void @fabs_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %c) {121; GCN-LABEL: @fabs_v2f16(122; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2123; GCN-NEXT: [[TMP2:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[TMP1]])124; GCN-NEXT: store <2 x half> [[TMP2]], ptr addrspace(3) [[C:%.*]], align 2125; GCN-NEXT: ret void126;127 %i0 = load half, ptr addrspace(3) %a, align 2128 %fabs0 = call half @llvm.fabs.f16(half %i0)129 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 1130 %i3 = load half, ptr addrspace(3) %arrayidx3, align 2131 %fabs1 = call half @llvm.fabs.f16(half %i3)132 store half %fabs0, ptr addrspace(3) %c, align 2133 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 1134 store half %fabs1, ptr addrspace(3) %arrayidx5, align 2135 ret void136}137 138define amdgpu_kernel void @test1_fabs_fma_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %b, ptr addrspace(3) %c, ptr addrspace(3) %d) {139; GCN-LABEL: @test1_fabs_fma_v2f16(140; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2141; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(3) [[B:%.*]], align 2142; GCN-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(3) [[C:%.*]], align 2143; GCN-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[TMP1]])144; GCN-NEXT: [[TMP5:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP4]], <2 x half> [[TMP2]], <2 x half> [[TMP3]])145; GCN-NEXT: store <2 x half> [[TMP5]], ptr addrspace(3) [[D:%.*]], align 2146; GCN-NEXT: ret void147;148 %i0 = load half, ptr addrspace(3) %a, align 2149 %i1 = load half, ptr addrspace(3) %b, align 2150 %i2 = load half, ptr addrspace(3) %c, align 2151 %i0.fabs = call half @llvm.fabs.f16(half %i0)152 153 %fma0 = call half @llvm.fma.f16(half %i0.fabs, half %i1, half %i2)154 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 1155 %i3 = load half, ptr addrspace(3) %arrayidx3, align 2156 %arrayidx4 = getelementptr inbounds half, ptr addrspace(3) %b, i64 1157 %i4 = load half, ptr addrspace(3) %arrayidx4, align 2158 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 1159 %i5 = load half, ptr addrspace(3) %arrayidx5, align 2160 %i3.fabs = call half @llvm.fabs.f16(half %i3)161 162 %fma1 = call half @llvm.fma.f16(half %i3.fabs, half %i4, half %i5)163 store half %fma0, ptr addrspace(3) %d, align 2164 %arrayidx6 = getelementptr inbounds half, ptr addrspace(3) %d, i64 1165 store half %fma1, ptr addrspace(3) %arrayidx6, align 2166 ret void167}168 169define amdgpu_kernel void @test1_fabs_scalar_fma_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %b, ptr addrspace(3) %c, ptr addrspace(3) %d) {170; GCN-LABEL: @test1_fabs_scalar_fma_v2f16(171; GCN-NEXT: [[I1:%.*]] = load half, ptr addrspace(3) [[B:%.*]], align 2172; GCN-NEXT: [[I1_FABS:%.*]] = call half @llvm.fabs.f16(half [[I1]])173; GCN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds half, ptr addrspace(3) [[B]], i64 1174; GCN-NEXT: [[I4:%.*]] = load half, ptr addrspace(3) [[ARRAYIDX4]], align 2175; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2176; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(3) [[C:%.*]], align 2177; GCN-NEXT: [[TMP3:%.*]] = insertelement <2 x half> poison, half [[I1_FABS]], i32 0178; GCN-NEXT: [[TMP4:%.*]] = insertelement <2 x half> [[TMP3]], half [[I4]], i32 1179; GCN-NEXT: [[TMP5:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP1]], <2 x half> [[TMP4]], <2 x half> [[TMP2]])180; GCN-NEXT: store <2 x half> [[TMP5]], ptr addrspace(3) [[D:%.*]], align 2181; GCN-NEXT: ret void182;183 %i0 = load half, ptr addrspace(3) %a, align 2184 %i1 = load half, ptr addrspace(3) %b, align 2185 %i2 = load half, ptr addrspace(3) %c, align 2186 %i1.fabs = call half @llvm.fabs.f16(half %i1)187 188 %fma0 = call half @llvm.fma.f16(half %i0, half %i1.fabs, half %i2)189 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 1190 %i3 = load half, ptr addrspace(3) %arrayidx3, align 2191 %arrayidx4 = getelementptr inbounds half, ptr addrspace(3) %b, i64 1192 %i4 = load half, ptr addrspace(3) %arrayidx4, align 2193 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 1194 %i5 = load half, ptr addrspace(3) %arrayidx5, align 2195 %fma1 = call half @llvm.fma.f16(half %i3, half %i4, half %i5)196 store half %fma0, ptr addrspace(3) %d, align 2197 %arrayidx6 = getelementptr inbounds half, ptr addrspace(3) %d, i64 1198 store half %fma1, ptr addrspace(3) %arrayidx6, align 2199 ret void200}201 202define amdgpu_kernel void @canonicalize_v2f16(ptr addrspace(3) %a, ptr addrspace(3) %c) {203; GCN-LABEL: @canonicalize_v2f16(204; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2205; GCN-NEXT: [[TMP2:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP1]])206; GCN-NEXT: store <2 x half> [[TMP2]], ptr addrspace(3) [[C:%.*]], align 2207; GCN-NEXT: ret void208;209 %i0 = load half, ptr addrspace(3) %a, align 2210 %canonicalize0 = call half @llvm.canonicalize.f16(half %i0)211 %arrayidx3 = getelementptr inbounds half, ptr addrspace(3) %a, i64 1212 %i3 = load half, ptr addrspace(3) %arrayidx3, align 2213 %canonicalize1 = call half @llvm.canonicalize.f16(half %i3)214 store half %canonicalize0, ptr addrspace(3) %c, align 2215 %arrayidx5 = getelementptr inbounds half, ptr addrspace(3) %c, i64 1216 store half %canonicalize1, ptr addrspace(3) %arrayidx5, align 2217 ret void218}219 220declare half @llvm.fabs.f16(half) #1221declare half @llvm.fma.f16(half, half, half) #1222declare half @llvm.canonicalize.f16(half) #1223 224attributes #0 = { nounwind }225attributes #1 = { nounwind readnone }226;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:227; GFX9: {{.*}}228; VI: {{.*}}229