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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s4 5define half @reduction_half4(<4 x half> %a) {6; GFX9-LABEL: @reduction_half4(7; GFX9-NEXT: entry:8; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[A:%.*]])9; GFX9-NEXT: ret half [[TMP0]]10;11; VI-LABEL: @reduction_half4(12; VI-NEXT: entry:13; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x half> [[A:%.*]], i64 014; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x half> [[A]], i64 115; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x half> [[A]], i64 216; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x half> [[A]], i64 317; VI-NEXT: [[ADD1:%.*]] = fadd fast half [[ELT1]], [[ELT0]]18; VI-NEXT: [[ADD2:%.*]] = fadd fast half [[ELT2]], [[ADD1]]19; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]20; VI-NEXT: ret half [[ADD3]]21;22entry:23 %elt0 = extractelement <4 x half> %a, i64 024 %elt1 = extractelement <4 x half> %a, i64 125 %elt2 = extractelement <4 x half> %a, i64 226 %elt3 = extractelement <4 x half> %a, i64 327 28 %add1 = fadd fast half %elt1, %elt029 %add2 = fadd fast half %elt2, %add130 %add3 = fadd fast half %elt3, %add231 32 ret half %add333}34 35define half @reduction_half8(<8 x half> %vec8) {36; GFX9-LABEL: @reduction_half8(37; GFX9-NEXT: entry:38; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> [[VEC8:%.*]])39; GFX9-NEXT: ret half [[TMP0]]40;41; VI-LABEL: @reduction_half8(42; VI-NEXT: entry:43; VI-NEXT: [[ELT0:%.*]] = extractelement <8 x half> [[VEC8:%.*]], i64 044; VI-NEXT: [[ELT1:%.*]] = extractelement <8 x half> [[VEC8]], i64 145; VI-NEXT: [[ELT2:%.*]] = extractelement <8 x half> [[VEC8]], i64 246; VI-NEXT: [[ELT3:%.*]] = extractelement <8 x half> [[VEC8]], i64 347; VI-NEXT: [[ELT4:%.*]] = extractelement <8 x half> [[VEC8]], i64 448; VI-NEXT: [[ELT5:%.*]] = extractelement <8 x half> [[VEC8]], i64 549; VI-NEXT: [[ELT6:%.*]] = extractelement <8 x half> [[VEC8]], i64 650; VI-NEXT: [[ELT7:%.*]] = extractelement <8 x half> [[VEC8]], i64 751; VI-NEXT: [[ADD1:%.*]] = fadd fast half [[ELT1]], [[ELT0]]52; VI-NEXT: [[ADD2:%.*]] = fadd fast half [[ELT2]], [[ADD1]]53; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]54; VI-NEXT: [[ADD4:%.*]] = fadd fast half [[ELT4]], [[ADD3]]55; VI-NEXT: [[ADD5:%.*]] = fadd fast half [[ELT5]], [[ADD4]]56; VI-NEXT: [[ADD6:%.*]] = fadd fast half [[ELT6]], [[ADD5]]57; VI-NEXT: [[ADD7:%.*]] = fadd fast half [[ELT7]], [[ADD6]]58; VI-NEXT: ret half [[ADD7]]59;60entry:61 %elt0 = extractelement <8 x half> %vec8, i64 062 %elt1 = extractelement <8 x half> %vec8, i64 163 %elt2 = extractelement <8 x half> %vec8, i64 264 %elt3 = extractelement <8 x half> %vec8, i64 365 %elt4 = extractelement <8 x half> %vec8, i64 466 %elt5 = extractelement <8 x half> %vec8, i64 567 %elt6 = extractelement <8 x half> %vec8, i64 668 %elt7 = extractelement <8 x half> %vec8, i64 769 70 %add1 = fadd fast half %elt1, %elt071 %add2 = fadd fast half %elt2, %add172 %add3 = fadd fast half %elt3, %add273 %add4 = fadd fast half %elt4, %add374 %add5 = fadd fast half %elt5, %add475 %add6 = fadd fast half %elt6, %add576 %add7 = fadd fast half %elt7, %add677 78 ret half %add779}80 81define half @reduction_half16(<16 x half> %vec16) {82; GFX9-LABEL: @reduction_half16(83; GFX9-NEXT: entry:84; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> [[VEC16:%.*]])85; GFX9-NEXT: ret half [[TMP0]]86;87; VI-LABEL: @reduction_half16(88; VI-NEXT: entry:89; VI-NEXT: [[ELT0:%.*]] = extractelement <16 x half> [[VEC16:%.*]], i64 090; VI-NEXT: [[ELT1:%.*]] = extractelement <16 x half> [[VEC16]], i64 191; VI-NEXT: [[ELT2:%.*]] = extractelement <16 x half> [[VEC16]], i64 292; VI-NEXT: [[ELT3:%.*]] = extractelement <16 x half> [[VEC16]], i64 393; VI-NEXT: [[ELT4:%.*]] = extractelement <16 x half> [[VEC16]], i64 494; VI-NEXT: [[ELT5:%.*]] = extractelement <16 x half> [[VEC16]], i64 595; VI-NEXT: [[ELT6:%.*]] = extractelement <16 x half> [[VEC16]], i64 696; VI-NEXT: [[ELT7:%.*]] = extractelement <16 x half> [[VEC16]], i64 797; VI-NEXT: [[ELT8:%.*]] = extractelement <16 x half> [[VEC16]], i64 898; VI-NEXT: [[ELT9:%.*]] = extractelement <16 x half> [[VEC16]], i64 999; VI-NEXT: [[ELT10:%.*]] = extractelement <16 x half> [[VEC16]], i64 10100; VI-NEXT: [[ELT11:%.*]] = extractelement <16 x half> [[VEC16]], i64 11101; VI-NEXT: [[ELT12:%.*]] = extractelement <16 x half> [[VEC16]], i64 12102; VI-NEXT: [[ELT13:%.*]] = extractelement <16 x half> [[VEC16]], i64 13103; VI-NEXT: [[ELT14:%.*]] = extractelement <16 x half> [[VEC16]], i64 14104; VI-NEXT: [[ELT15:%.*]] = extractelement <16 x half> [[VEC16]], i64 15105; VI-NEXT: [[ADD1:%.*]] = fadd fast half [[ELT1]], [[ELT0]]106; VI-NEXT: [[ADD2:%.*]] = fadd fast half [[ELT2]], [[ADD1]]107; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]108; VI-NEXT: [[ADD4:%.*]] = fadd fast half [[ELT4]], [[ADD3]]109; VI-NEXT: [[ADD5:%.*]] = fadd fast half [[ELT5]], [[ADD4]]110; VI-NEXT: [[ADD6:%.*]] = fadd fast half [[ELT6]], [[ADD5]]111; VI-NEXT: [[ADD7:%.*]] = fadd fast half [[ELT7]], [[ADD6]]112; VI-NEXT: [[ADD8:%.*]] = fadd fast half [[ELT8]], [[ADD7]]113; VI-NEXT: [[ADD9:%.*]] = fadd fast half [[ELT9]], [[ADD8]]114; VI-NEXT: [[ADD10:%.*]] = fadd fast half [[ELT10]], [[ADD9]]115; VI-NEXT: [[ADD11:%.*]] = fadd fast half [[ELT11]], [[ADD10]]116; VI-NEXT: [[ADD12:%.*]] = fadd fast half [[ELT12]], [[ADD11]]117; VI-NEXT: [[ADD13:%.*]] = fadd fast half [[ELT13]], [[ADD12]]118; VI-NEXT: [[ADD14:%.*]] = fadd fast half [[ELT14]], [[ADD13]]119; VI-NEXT: [[OP_RDX:%.*]] = fadd fast half [[ELT15]], [[ADD14]]120; VI-NEXT: ret half [[OP_RDX]]121;122entry:123 %elt0 = extractelement <16 x half> %vec16, i64 0124 %elt1 = extractelement <16 x half> %vec16, i64 1125 %elt2 = extractelement <16 x half> %vec16, i64 2126 %elt3 = extractelement <16 x half> %vec16, i64 3127 %elt4 = extractelement <16 x half> %vec16, i64 4128 %elt5 = extractelement <16 x half> %vec16, i64 5129 %elt6 = extractelement <16 x half> %vec16, i64 6130 %elt7 = extractelement <16 x half> %vec16, i64 7131 %elt8 = extractelement <16 x half> %vec16, i64 8132 %elt9 = extractelement <16 x half> %vec16, i64 9133 %elt10 = extractelement <16 x half> %vec16, i64 10134 %elt11 = extractelement <16 x half> %vec16, i64 11135 %elt12 = extractelement <16 x half> %vec16, i64 12136 %elt13 = extractelement <16 x half> %vec16, i64 13137 %elt14 = extractelement <16 x half> %vec16, i64 14138 %elt15 = extractelement <16 x half> %vec16, i64 15139 140 %add1 = fadd fast half %elt1, %elt0141 %add2 = fadd fast half %elt2, %add1142 %add3 = fadd fast half %elt3, %add2143 %add4 = fadd fast half %elt4, %add3144 %add5 = fadd fast half %elt5, %add4145 %add6 = fadd fast half %elt6, %add5146 %add7 = fadd fast half %elt7, %add6147 %add8 = fadd fast half %elt8, %add7148 %add9 = fadd fast half %elt9, %add8149 %add10 = fadd fast half %elt10, %add9150 %add11 = fadd fast half %elt11, %add10151 %add12 = fadd fast half %elt12, %add11152 %add13 = fadd fast half %elt13, %add12153 %add14 = fadd fast half %elt14, %add13154 %add15 = fadd fast half %elt15, %add14155 156 ret half %add15157}158 159; FIXME: support vectorization;160define half @reduction_sub_half4(<4 x half> %a) {161; GCN-LABEL: @reduction_sub_half4(162; GCN-NEXT: entry:163; GCN-NEXT: [[ELT0:%.*]] = extractelement <4 x half> [[A:%.*]], i64 0164; GCN-NEXT: [[ELT1:%.*]] = extractelement <4 x half> [[A]], i64 1165; GCN-NEXT: [[ELT2:%.*]] = extractelement <4 x half> [[A]], i64 2166; GCN-NEXT: [[ELT3:%.*]] = extractelement <4 x half> [[A]], i64 3167; GCN-NEXT: [[ADD1:%.*]] = fsub fast half [[ELT1]], [[ELT0]]168; GCN-NEXT: [[ADD2:%.*]] = fsub fast half [[ELT2]], [[ADD1]]169; GCN-NEXT: [[ADD3:%.*]] = fsub fast half [[ELT3]], [[ADD2]]170; GCN-NEXT: ret half [[ADD3]]171;172entry:173 %elt0 = extractelement <4 x half> %a, i64 0174 %elt1 = extractelement <4 x half> %a, i64 1175 %elt2 = extractelement <4 x half> %a, i64 2176 %elt3 = extractelement <4 x half> %a, i64 3177 178 %add1 = fsub fast half %elt1, %elt0179 %add2 = fsub fast half %elt2, %add1180 %add3 = fsub fast half %elt3, %add2181 182 ret half %add3183}184 185define i16 @reduction_v4i16(<4 x i16> %a) {186; GFX9-LABEL: @reduction_v4i16(187; GFX9-NEXT: entry:188; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[A:%.*]])189; GFX9-NEXT: ret i16 [[TMP0]]190;191; VI-LABEL: @reduction_v4i16(192; VI-NEXT: entry:193; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x i16> [[A:%.*]], i64 0194; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[A]], i64 1195; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[A]], i64 2196; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[A]], i64 3197; VI-NEXT: [[ADD1:%.*]] = add i16 [[ELT1]], [[ELT0]]198; VI-NEXT: [[ADD2:%.*]] = add i16 [[ELT2]], [[ADD1]]199; VI-NEXT: [[ADD3:%.*]] = add i16 [[ELT3]], [[ADD2]]200; VI-NEXT: ret i16 [[ADD3]]201;202entry:203 %elt0 = extractelement <4 x i16> %a, i64 0204 %elt1 = extractelement <4 x i16> %a, i64 1205 %elt2 = extractelement <4 x i16> %a, i64 2206 %elt3 = extractelement <4 x i16> %a, i64 3207 208 %add1 = add i16 %elt1, %elt0209 %add2 = add i16 %elt2, %add1210 %add3 = add i16 %elt3, %add2211 212 ret i16 %add3213}214 215define i16 @reduction_v8i16(<8 x i16> %vec8) {216; GFX9-LABEL: @reduction_v8i16(217; GFX9-NEXT: entry:218; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[VEC8:%.*]])219; GFX9-NEXT: ret i16 [[TMP0]]220;221; VI-LABEL: @reduction_v8i16(222; VI-NEXT: entry:223; VI-NEXT: [[ELT0:%.*]] = extractelement <8 x i16> [[VEC8:%.*]], i64 0224; VI-NEXT: [[ELT1:%.*]] = extractelement <8 x i16> [[VEC8]], i64 1225; VI-NEXT: [[ELT2:%.*]] = extractelement <8 x i16> [[VEC8]], i64 2226; VI-NEXT: [[ELT3:%.*]] = extractelement <8 x i16> [[VEC8]], i64 3227; VI-NEXT: [[ELT4:%.*]] = extractelement <8 x i16> [[VEC8]], i64 4228; VI-NEXT: [[ELT5:%.*]] = extractelement <8 x i16> [[VEC8]], i64 5229; VI-NEXT: [[ELT6:%.*]] = extractelement <8 x i16> [[VEC8]], i64 6230; VI-NEXT: [[ELT7:%.*]] = extractelement <8 x i16> [[VEC8]], i64 7231; VI-NEXT: [[ADD1:%.*]] = add i16 [[ELT1]], [[ELT0]]232; VI-NEXT: [[ADD2:%.*]] = add i16 [[ELT2]], [[ADD1]]233; VI-NEXT: [[ADD3:%.*]] = add i16 [[ELT3]], [[ADD2]]234; VI-NEXT: [[ADD4:%.*]] = add i16 [[ELT4]], [[ADD3]]235; VI-NEXT: [[ADD5:%.*]] = add i16 [[ELT5]], [[ADD4]]236; VI-NEXT: [[ADD6:%.*]] = add i16 [[ELT6]], [[ADD5]]237; VI-NEXT: [[ADD7:%.*]] = add i16 [[ELT7]], [[ADD6]]238; VI-NEXT: ret i16 [[ADD7]]239;240entry:241 %elt0 = extractelement <8 x i16> %vec8, i64 0242 %elt1 = extractelement <8 x i16> %vec8, i64 1243 %elt2 = extractelement <8 x i16> %vec8, i64 2244 %elt3 = extractelement <8 x i16> %vec8, i64 3245 %elt4 = extractelement <8 x i16> %vec8, i64 4246 %elt5 = extractelement <8 x i16> %vec8, i64 5247 %elt6 = extractelement <8 x i16> %vec8, i64 6248 %elt7 = extractelement <8 x i16> %vec8, i64 7249 250 %add1 = add i16 %elt1, %elt0251 %add2 = add i16 %elt2, %add1252 %add3 = add i16 %elt3, %add2253 %add4 = add i16 %elt4, %add3254 %add5 = add i16 %elt5, %add4255 %add6 = add i16 %elt6, %add5256 %add7 = add i16 %elt7, %add6257 258 ret i16 %add7259}260 261define i16 @reduction_umin_v4i16(<4 x i16> %vec4) {262; GFX9-LABEL: @reduction_umin_v4i16(263; GFX9-NEXT: entry:264; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> [[VEC4:%.*]])265; GFX9-NEXT: ret i16 [[TMP0]]266;267; VI-LABEL: @reduction_umin_v4i16(268; VI-NEXT: entry:269; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x i16> [[VEC4:%.*]], i64 0270; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1271; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2272; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3273; VI-NEXT: [[CMP1:%.*]] = icmp ult i16 [[ELT1]], [[ELT0]]274; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]275; VI-NEXT: [[CMP2:%.*]] = icmp ult i16 [[ELT2]], [[MIN1]]276; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MIN1]]277; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT3]], [[MIN2]]278; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]279; VI-NEXT: ret i16 [[MIN3]]280;281entry:282 %elt0 = extractelement <4 x i16> %vec4, i64 0283 %elt1 = extractelement <4 x i16> %vec4, i64 1284 %elt2 = extractelement <4 x i16> %vec4, i64 2285 %elt3 = extractelement <4 x i16> %vec4, i64 3286 287 %cmp1 = icmp ult i16 %elt1, %elt0288 %min1 = select i1 %cmp1, i16 %elt1, i16 %elt0289 %cmp2 = icmp ult i16 %elt2, %min1290 %min2 = select i1 %cmp2, i16 %elt2, i16 %min1291 %cmp3 = icmp ult i16 %elt3, %min2292 %min3 = select i1 %cmp3, i16 %elt3, i16 %min2293 294 ret i16 %min3295}296 297define i16 @reduction_icmp_v8i16(<8 x i16> %vec8) {298; GFX9-LABEL: @reduction_icmp_v8i16(299; GFX9-NEXT: entry:300; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> [[VEC8:%.*]])301; GFX9-NEXT: ret i16 [[TMP0]]302;303; VI-LABEL: @reduction_icmp_v8i16(304; VI-NEXT: entry:305; VI-NEXT: [[ELT0:%.*]] = extractelement <8 x i16> [[VEC8:%.*]], i64 0306; VI-NEXT: [[ELT1:%.*]] = extractelement <8 x i16> [[VEC8]], i64 1307; VI-NEXT: [[ELT2:%.*]] = extractelement <8 x i16> [[VEC8]], i64 2308; VI-NEXT: [[ELT3:%.*]] = extractelement <8 x i16> [[VEC8]], i64 3309; VI-NEXT: [[ELT4:%.*]] = extractelement <8 x i16> [[VEC8]], i64 4310; VI-NEXT: [[ELT5:%.*]] = extractelement <8 x i16> [[VEC8]], i64 5311; VI-NEXT: [[ELT6:%.*]] = extractelement <8 x i16> [[VEC8]], i64 6312; VI-NEXT: [[ELT7:%.*]] = extractelement <8 x i16> [[VEC8]], i64 7313; VI-NEXT: [[CMP0:%.*]] = icmp ult i16 [[ELT1]], [[ELT0]]314; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP0]], i16 [[ELT1]], i16 [[ELT0]]315; VI-NEXT: [[CMP1:%.*]] = icmp ult i16 [[ELT2]], [[MIN1]]316; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP1]], i16 [[ELT2]], i16 [[MIN1]]317; VI-NEXT: [[CMP2:%.*]] = icmp ult i16 [[ELT3]], [[MIN2]]318; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]319; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]320; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]321; VI-NEXT: [[CMP4:%.*]] = icmp ult i16 [[ELT5]], [[MIN4]]322; VI-NEXT: [[MIN5:%.*]] = select i1 [[CMP4]], i16 [[ELT5]], i16 [[MIN4]]323; VI-NEXT: [[CMP5:%.*]] = icmp ult i16 [[ELT6]], [[MIN5]]324; VI-NEXT: [[MIN6:%.*]] = select i1 [[CMP5]], i16 [[ELT6]], i16 [[MIN5]]325; VI-NEXT: [[CMP6:%.*]] = icmp ult i16 [[ELT7]], [[MIN6]]326; VI-NEXT: [[MIN7:%.*]] = select i1 [[CMP6]], i16 [[ELT7]], i16 [[MIN6]]327; VI-NEXT: ret i16 [[MIN7]]328;329entry:330 %elt0 = extractelement <8 x i16> %vec8, i64 0331 %elt1 = extractelement <8 x i16> %vec8, i64 1332 %elt2 = extractelement <8 x i16> %vec8, i64 2333 %elt3 = extractelement <8 x i16> %vec8, i64 3334 %elt4 = extractelement <8 x i16> %vec8, i64 4335 %elt5 = extractelement <8 x i16> %vec8, i64 5336 %elt6 = extractelement <8 x i16> %vec8, i64 6337 %elt7 = extractelement <8 x i16> %vec8, i64 7338 339 %cmp0 = icmp ult i16 %elt1, %elt0340 %min1 = select i1 %cmp0, i16 %elt1, i16 %elt0341 %cmp1 = icmp ult i16 %elt2, %min1342 %min2 = select i1 %cmp1, i16 %elt2, i16 %min1343 %cmp2 = icmp ult i16 %elt3, %min2344 %min3 = select i1 %cmp2, i16 %elt3, i16 %min2345 346 %cmp3 = icmp ult i16 %elt4, %min3347 %min4 = select i1 %cmp3, i16 %elt4, i16 %min3348 %cmp4 = icmp ult i16 %elt5, %min4349 %min5 = select i1 %cmp4, i16 %elt5, i16 %min4350 351 %cmp5 = icmp ult i16 %elt6, %min5352 %min6 = select i1 %cmp5, i16 %elt6, i16 %min5353 %cmp6 = icmp ult i16 %elt7, %min6354 %min7 = select i1 %cmp6, i16 %elt7, i16 %min6355 356 ret i16 %min7357}358 359define i16 @reduction_smin_v16i16(<16 x i16> %vec16) {360; GFX9-LABEL: @reduction_smin_v16i16(361; GFX9-NEXT: entry:362; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> [[VEC16:%.*]])363; GFX9-NEXT: ret i16 [[TMP0]]364;365; VI-LABEL: @reduction_smin_v16i16(366; VI-NEXT: entry:367; VI-NEXT: [[ELT0:%.*]] = extractelement <16 x i16> [[VEC16:%.*]], i64 0368; VI-NEXT: [[ELT1:%.*]] = extractelement <16 x i16> [[VEC16]], i64 1369; VI-NEXT: [[ELT2:%.*]] = extractelement <16 x i16> [[VEC16]], i64 2370; VI-NEXT: [[ELT3:%.*]] = extractelement <16 x i16> [[VEC16]], i64 3371; VI-NEXT: [[ELT4:%.*]] = extractelement <16 x i16> [[VEC16]], i64 4372; VI-NEXT: [[ELT5:%.*]] = extractelement <16 x i16> [[VEC16]], i64 5373; VI-NEXT: [[ELT6:%.*]] = extractelement <16 x i16> [[VEC16]], i64 6374; VI-NEXT: [[ELT7:%.*]] = extractelement <16 x i16> [[VEC16]], i64 7375; VI-NEXT: [[ELT8:%.*]] = extractelement <16 x i16> [[VEC16]], i64 8376; VI-NEXT: [[ELT9:%.*]] = extractelement <16 x i16> [[VEC16]], i64 9377; VI-NEXT: [[ELT10:%.*]] = extractelement <16 x i16> [[VEC16]], i64 10378; VI-NEXT: [[ELT11:%.*]] = extractelement <16 x i16> [[VEC16]], i64 11379; VI-NEXT: [[ELT12:%.*]] = extractelement <16 x i16> [[VEC16]], i64 12380; VI-NEXT: [[ELT13:%.*]] = extractelement <16 x i16> [[VEC16]], i64 13381; VI-NEXT: [[ELT14:%.*]] = extractelement <16 x i16> [[VEC16]], i64 14382; VI-NEXT: [[ELT15:%.*]] = extractelement <16 x i16> [[VEC16]], i64 15383; VI-NEXT: [[CMP0:%.*]] = icmp slt i16 [[ELT1]], [[ELT0]]384; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP0]], i16 [[ELT1]], i16 [[ELT0]]385; VI-NEXT: [[CMP1:%.*]] = icmp slt i16 [[ELT2]], [[MIN1]]386; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP1]], i16 [[ELT2]], i16 [[MIN1]]387; VI-NEXT: [[CMP2:%.*]] = icmp slt i16 [[ELT3]], [[MIN2]]388; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]389; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]390; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]391; VI-NEXT: [[CMP4:%.*]] = icmp slt i16 [[ELT5]], [[MIN4]]392; VI-NEXT: [[MIN5:%.*]] = select i1 [[CMP4]], i16 [[ELT5]], i16 [[MIN4]]393; VI-NEXT: [[CMP5:%.*]] = icmp slt i16 [[ELT6]], [[MIN5]]394; VI-NEXT: [[MIN6:%.*]] = select i1 [[CMP5]], i16 [[ELT6]], i16 [[MIN5]]395; VI-NEXT: [[CMP6:%.*]] = icmp slt i16 [[ELT7]], [[MIN6]]396; VI-NEXT: [[MIN7:%.*]] = select i1 [[CMP6]], i16 [[ELT7]], i16 [[MIN6]]397; VI-NEXT: [[CMP7:%.*]] = icmp slt i16 [[ELT8]], [[MIN7]]398; VI-NEXT: [[MIN8:%.*]] = select i1 [[CMP7]], i16 [[ELT8]], i16 [[MIN7]]399; VI-NEXT: [[CMP8:%.*]] = icmp slt i16 [[ELT9]], [[MIN8]]400; VI-NEXT: [[MIN9:%.*]] = select i1 [[CMP8]], i16 [[ELT9]], i16 [[MIN8]]401; VI-NEXT: [[CMP9:%.*]] = icmp slt i16 [[ELT10]], [[MIN9]]402; VI-NEXT: [[MIN10:%.*]] = select i1 [[CMP9]], i16 [[ELT10]], i16 [[MIN9]]403; VI-NEXT: [[CMP10:%.*]] = icmp slt i16 [[ELT11]], [[MIN10]]404; VI-NEXT: [[MIN11:%.*]] = select i1 [[CMP10]], i16 [[ELT11]], i16 [[MIN10]]405; VI-NEXT: [[CMP11:%.*]] = icmp slt i16 [[ELT12]], [[MIN11]]406; VI-NEXT: [[MIN12:%.*]] = select i1 [[CMP11]], i16 [[ELT12]], i16 [[MIN11]]407; VI-NEXT: [[CMP12:%.*]] = icmp slt i16 [[ELT13]], [[MIN12]]408; VI-NEXT: [[MIN13:%.*]] = select i1 [[CMP12]], i16 [[ELT13]], i16 [[MIN12]]409; VI-NEXT: [[CMP13:%.*]] = icmp slt i16 [[ELT14]], [[MIN13]]410; VI-NEXT: [[MIN14:%.*]] = select i1 [[CMP13]], i16 [[ELT14]], i16 [[MIN13]]411; VI-NEXT: [[CMP14:%.*]] = icmp slt i16 [[ELT15]], [[MIN14]]412; VI-NEXT: [[MIN15:%.*]] = select i1 [[CMP14]], i16 [[ELT15]], i16 [[MIN14]]413; VI-NEXT: ret i16 [[MIN15]]414;415entry:416 %elt0 = extractelement <16 x i16> %vec16, i64 0417 %elt1 = extractelement <16 x i16> %vec16, i64 1418 %elt2 = extractelement <16 x i16> %vec16, i64 2419 %elt3 = extractelement <16 x i16> %vec16, i64 3420 %elt4 = extractelement <16 x i16> %vec16, i64 4421 %elt5 = extractelement <16 x i16> %vec16, i64 5422 %elt6 = extractelement <16 x i16> %vec16, i64 6423 %elt7 = extractelement <16 x i16> %vec16, i64 7424 425 %elt8 = extractelement <16 x i16> %vec16, i64 8426 %elt9 = extractelement <16 x i16> %vec16, i64 9427 %elt10 = extractelement <16 x i16> %vec16, i64 10428 %elt11 = extractelement <16 x i16> %vec16, i64 11429 %elt12 = extractelement <16 x i16> %vec16, i64 12430 %elt13 = extractelement <16 x i16> %vec16, i64 13431 %elt14 = extractelement <16 x i16> %vec16, i64 14432 %elt15 = extractelement <16 x i16> %vec16, i64 15433 434 %cmp0 = icmp slt i16 %elt1, %elt0435 %min1 = select i1 %cmp0, i16 %elt1, i16 %elt0436 %cmp1 = icmp slt i16 %elt2, %min1437 %min2 = select i1 %cmp1, i16 %elt2, i16 %min1438 %cmp2 = icmp slt i16 %elt3, %min2439 %min3 = select i1 %cmp2, i16 %elt3, i16 %min2440 441 %cmp3 = icmp slt i16 %elt4, %min3442 %min4 = select i1 %cmp3, i16 %elt4, i16 %min3443 %cmp4 = icmp slt i16 %elt5, %min4444 %min5 = select i1 %cmp4, i16 %elt5, i16 %min4445 446 %cmp5 = icmp slt i16 %elt6, %min5447 %min6 = select i1 %cmp5, i16 %elt6, i16 %min5448 %cmp6 = icmp slt i16 %elt7, %min6449 %min7 = select i1 %cmp6, i16 %elt7, i16 %min6450 451 %cmp7 = icmp slt i16 %elt8, %min7452 %min8 = select i1 %cmp7, i16 %elt8, i16 %min7453 %cmp8 = icmp slt i16 %elt9, %min8454 %min9 = select i1 %cmp8, i16 %elt9, i16 %min8455 456 %cmp9 = icmp slt i16 %elt10, %min9457 %min10 = select i1 %cmp9, i16 %elt10, i16 %min9458 %cmp10 = icmp slt i16 %elt11, %min10459 %min11 = select i1 %cmp10, i16 %elt11, i16 %min10460 461 %cmp11 = icmp slt i16 %elt12, %min11462 %min12 = select i1 %cmp11, i16 %elt12, i16 %min11463 %cmp12 = icmp slt i16 %elt13, %min12464 %min13 = select i1 %cmp12, i16 %elt13, i16 %min12465 466 %cmp13 = icmp slt i16 %elt14, %min13467 %min14 = select i1 %cmp13, i16 %elt14, i16 %min13468 %cmp14 = icmp slt i16 %elt15, %min14469 %min15 = select i1 %cmp14, i16 %elt15, i16 %min14470 471 472 ret i16 %min15473}474 475define i16 @reduction_umax_v4i16(<4 x i16> %vec4) {476; GFX9-LABEL: @reduction_umax_v4i16(477; GFX9-NEXT: entry:478; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[VEC4:%.*]])479; GFX9-NEXT: ret i16 [[TMP0]]480;481; VI-LABEL: @reduction_umax_v4i16(482; VI-NEXT: entry:483; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x i16> [[VEC4:%.*]], i64 0484; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1485; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2486; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3487; VI-NEXT: [[CMP1:%.*]] = icmp ugt i16 [[ELT1]], [[ELT0]]488; VI-NEXT: [[MAX1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]489; VI-NEXT: [[CMP2:%.*]] = icmp ugt i16 [[ELT2]], [[MAX1]]490; VI-NEXT: [[MAX2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MAX1]]491; VI-NEXT: [[CMP3:%.*]] = icmp ugt i16 [[ELT3]], [[MAX2]]492; VI-NEXT: [[MAX3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MAX2]]493; VI-NEXT: ret i16 [[MAX3]]494;495entry:496 %elt0 = extractelement <4 x i16> %vec4, i64 0497 %elt1 = extractelement <4 x i16> %vec4, i64 1498 %elt2 = extractelement <4 x i16> %vec4, i64 2499 %elt3 = extractelement <4 x i16> %vec4, i64 3500 501 %cmp1 = icmp ugt i16 %elt1, %elt0502 %max1 = select i1 %cmp1, i16 %elt1, i16 %elt0503 %cmp2 = icmp ugt i16 %elt2, %max1504 %max2 = select i1 %cmp2, i16 %elt2, i16 %max1505 %cmp3 = icmp ugt i16 %elt3, %max2506 %max3 = select i1 %cmp3, i16 %elt3, i16 %max2507 508 ret i16 %max3509}510 511define i16 @reduction_smax_v4i16(<4 x i16> %vec4) {512; GFX9-LABEL: @reduction_smax_v4i16(513; GFX9-NEXT: entry:514; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[VEC4:%.*]])515; GFX9-NEXT: ret i16 [[TMP0]]516;517; VI-LABEL: @reduction_smax_v4i16(518; VI-NEXT: entry:519; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x i16> [[VEC4:%.*]], i64 0520; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1521; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2522; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3523; VI-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[ELT1]], [[ELT0]]524; VI-NEXT: [[MAX1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]525; VI-NEXT: [[CMP2:%.*]] = icmp sgt i16 [[ELT2]], [[MAX1]]526; VI-NEXT: [[MAX2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MAX1]]527; VI-NEXT: [[CMP3:%.*]] = icmp sgt i16 [[ELT3]], [[MAX2]]528; VI-NEXT: [[MAX3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MAX2]]529; VI-NEXT: ret i16 [[MAX3]]530;531entry:532 %elt0 = extractelement <4 x i16> %vec4, i64 0533 %elt1 = extractelement <4 x i16> %vec4, i64 1534 %elt2 = extractelement <4 x i16> %vec4, i64 2535 %elt3 = extractelement <4 x i16> %vec4, i64 3536 537 %cmp1 = icmp sgt i16 %elt1, %elt0538 %max1 = select i1 %cmp1, i16 %elt1, i16 %elt0539 %cmp2 = icmp sgt i16 %elt2, %max1540 %max2 = select i1 %cmp2, i16 %elt2, i16 %max1541 %cmp3 = icmp sgt i16 %elt3, %max2542 %max3 = select i1 %cmp3, i16 %elt3, i16 %max2543 544 ret i16 %max3545}546 547; FIXME: Use fmaxnum intrinsics to match what InstCombine creates for fcmp+select548; with fastmath on the select.549define half @reduction_fmax_v4half(<4 x half> %vec4) {550; GCN-LABEL: @reduction_fmax_v4half(551; GCN-NEXT: entry:552; GCN-NEXT: [[ELT0:%.*]] = extractelement <4 x half> [[VEC4:%.*]], i64 0553; GCN-NEXT: [[ELT1:%.*]] = extractelement <4 x half> [[VEC4]], i64 1554; GCN-NEXT: [[ELT2:%.*]] = extractelement <4 x half> [[VEC4]], i64 2555; GCN-NEXT: [[ELT3:%.*]] = extractelement <4 x half> [[VEC4]], i64 3556; GCN-NEXT: [[CMP1:%.*]] = fcmp fast ogt half [[ELT1]], [[ELT0]]557; GCN-NEXT: [[MAX1:%.*]] = select i1 [[CMP1]], half [[ELT1]], half [[ELT0]]558; GCN-NEXT: [[CMP2:%.*]] = fcmp fast ogt half [[ELT2]], [[MAX1]]559; GCN-NEXT: [[MAX2:%.*]] = select i1 [[CMP2]], half [[ELT2]], half [[MAX1]]560; GCN-NEXT: [[CMP3:%.*]] = fcmp fast ogt half [[ELT3]], [[MAX2]]561; GCN-NEXT: [[MAX3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MAX2]]562; GCN-NEXT: ret half [[MAX3]]563;564entry:565 %elt0 = extractelement <4 x half> %vec4, i64 0566 %elt1 = extractelement <4 x half> %vec4, i64 1567 %elt2 = extractelement <4 x half> %vec4, i64 2568 %elt3 = extractelement <4 x half> %vec4, i64 3569 570 %cmp1 = fcmp fast ogt half %elt1, %elt0571 %max1 = select i1 %cmp1, half %elt1, half %elt0572 %cmp2 = fcmp fast ogt half %elt2, %max1573 %max2 = select i1 %cmp2, half %elt2, half %max1574 %cmp3 = fcmp fast ogt half %elt3, %max2575 %max3 = select i1 %cmp3, half %elt3, half %max2576 577 ret half %max3578}579 580; FIXME: Use fmaxnum intrinsics to match what InstCombine creates for fcmp+select581; with fastmath on the select.582define half @reduction_fmin_v4half(<4 x half> %vec4) {583; GCN-LABEL: @reduction_fmin_v4half(584; GCN-NEXT: entry:585; GCN-NEXT: [[ELT0:%.*]] = extractelement <4 x half> [[VEC4:%.*]], i64 0586; GCN-NEXT: [[ELT1:%.*]] = extractelement <4 x half> [[VEC4]], i64 1587; GCN-NEXT: [[ELT2:%.*]] = extractelement <4 x half> [[VEC4]], i64 2588; GCN-NEXT: [[ELT3:%.*]] = extractelement <4 x half> [[VEC4]], i64 3589; GCN-NEXT: [[CMP1:%.*]] = fcmp fast olt half [[ELT1]], [[ELT0]]590; GCN-NEXT: [[MIN1:%.*]] = select i1 [[CMP1]], half [[ELT1]], half [[ELT0]]591; GCN-NEXT: [[CMP2:%.*]] = fcmp fast olt half [[ELT2]], [[MIN1]]592; GCN-NEXT: [[MIN2:%.*]] = select i1 [[CMP2]], half [[ELT2]], half [[MIN1]]593; GCN-NEXT: [[CMP3:%.*]] = fcmp fast olt half [[ELT3]], [[MIN2]]594; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]595; GCN-NEXT: ret half [[MIN3]]596;597entry:598 %elt0 = extractelement <4 x half> %vec4, i64 0599 %elt1 = extractelement <4 x half> %vec4, i64 1600 %elt2 = extractelement <4 x half> %vec4, i64 2601 %elt3 = extractelement <4 x half> %vec4, i64 3602 603 %cmp1 = fcmp fast olt half %elt1, %elt0604 %min1 = select i1 %cmp1, half %elt1, half %elt0605 %cmp2 = fcmp fast olt half %elt2, %min1606 %min2 = select i1 %cmp2, half %elt2, half %min1607 %cmp3 = fcmp fast olt half %elt3, %min2608 %min3 = select i1 %cmp3, half %elt3, half %min2609 610 ret half %min3611}612 613; Tests to make sure reduction does not kick in. vega does not support packed math for types larger than 16 bits.614define float @reduction_v4float(<4 x float> %a) {615; GCN-LABEL: @reduction_v4float(616; GCN-NEXT: entry:617; GCN-NEXT: [[ELT0:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0618; GCN-NEXT: [[ELT1:%.*]] = extractelement <4 x float> [[A]], i64 1619; GCN-NEXT: [[ELT2:%.*]] = extractelement <4 x float> [[A]], i64 2620; GCN-NEXT: [[ELT3:%.*]] = extractelement <4 x float> [[A]], i64 3621; GCN-NEXT: [[ADD1:%.*]] = fadd fast float [[ELT1]], [[ELT0]]622; GCN-NEXT: [[ADD2:%.*]] = fadd fast float [[ELT2]], [[ADD1]]623; GCN-NEXT: [[ADD3:%.*]] = fadd fast float [[ELT3]], [[ADD2]]624; GCN-NEXT: ret float [[ADD3]]625;626entry:627 %elt0 = extractelement <4 x float> %a, i64 0628 %elt1 = extractelement <4 x float> %a, i64 1629 %elt2 = extractelement <4 x float> %a, i64 2630 %elt3 = extractelement <4 x float> %a, i64 3631 632 %add1 = fadd fast float %elt1, %elt0633 %add2 = fadd fast float %elt2, %add1634 %add3 = fadd fast float %elt3, %add2635 636 ret float %add3637}638