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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name I --version 62; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX8 %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX9 %s6 7; FIXME: Should not vectorize on gfx88 9define void @fadd_combine_v2f16(ptr addrspace(1) %arg) {10; GCN-LABEL: define void @fadd_combine_v2f16(11; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {12; GCN-NEXT: [[BB:.*:]]13; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()14; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i6415; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]16; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 217; GCN-NEXT: [[TMP1:%.*]] = fadd <2 x half> [[TMP0]], splat (half 0xH3C00)18; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 219; GCN-NEXT: ret void20;21bb:22 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()23 %tmp1 = zext i32 %tmp to i6424 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp125 %tmp3 = load half, ptr addrspace(1) %tmp2, align 226 %tmp4 = fadd half %tmp3, 1.000000e+0027 store half %tmp4, ptr addrspace(1) %tmp2, align 228 %tmp5 = add nuw nsw i64 %tmp1, 129 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp530 %tmp7 = load half, ptr addrspace(1) %tmp6, align 231 %tmp8 = fadd half %tmp7, 1.000000e+0032 store half %tmp8, ptr addrspace(1) %tmp6, align 233 ret void34}35 36; FIXME: Should not vectorize on gfx837define void @fsub_combine_v2f16(ptr addrspace(1) %arg) {38; GCN-LABEL: define void @fsub_combine_v2f16(39; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {40; GCN-NEXT: [[BB:.*:]]41; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()42; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i6443; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]44; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 245; GCN-NEXT: [[TMP1:%.*]] = fsub <2 x half> [[TMP0]], splat (half 0xH3C00)46; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 247; GCN-NEXT: ret void48;49bb:50 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()51 %tmp1 = zext i32 %tmp to i6452 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp153 %tmp3 = load half, ptr addrspace(1) %tmp2, align 254 %tmp4 = fsub half %tmp3, 1.000000e+0055 store half %tmp4, ptr addrspace(1) %tmp2, align 256 %tmp5 = add nuw nsw i64 %tmp1, 157 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp558 %tmp7 = load half, ptr addrspace(1) %tmp6, align 259 %tmp8 = fsub half %tmp7, 1.000000e+0060 store half %tmp8, ptr addrspace(1) %tmp6, align 261 ret void62}63 64; FIXME: Should not vectorize on gfx865define void @fmul_combine_v2f16(ptr addrspace(1) %arg) {66; GCN-LABEL: define void @fmul_combine_v2f16(67; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {68; GCN-NEXT: [[BB:.*:]]69; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()70; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i6471; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]72; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 273; GCN-NEXT: [[TMP1:%.*]] = fmul <2 x half> [[TMP0]], splat (half 0xH3C00)74; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 275; GCN-NEXT: ret void76;77bb:78 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()79 %tmp1 = zext i32 %tmp to i6480 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp181 %tmp3 = load half, ptr addrspace(1) %tmp2, align 282 %tmp4 = fmul half %tmp3, 1.000000e+0083 store half %tmp4, ptr addrspace(1) %tmp2, align 284 %tmp5 = add nuw nsw i64 %tmp1, 185 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp586 %tmp7 = load half, ptr addrspace(1) %tmp6, align 287 %tmp8 = fmul half %tmp7, 1.000000e+0088 store half %tmp8, ptr addrspace(1) %tmp6, align 289 ret void90}91 92define void @fdiv_combine_v2f16(ptr addrspace(1) %arg) {93; GCN-LABEL: define void @fdiv_combine_v2f16(94; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {95; GCN-NEXT: [[BB:.*:]]96; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()97; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i6498; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]99; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2100; GCN-NEXT: [[TMP1:%.*]] = fdiv <2 x half> [[TMP0]], splat (half 0xH3C00)101; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2102; GCN-NEXT: ret void103;104bb:105 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()106 %tmp1 = zext i32 %tmp to i64107 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1108 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2109 %tmp4 = fdiv half %tmp3, 1.000000e+00110 store half %tmp4, ptr addrspace(1) %tmp2, align 2111 %tmp5 = add nuw nsw i64 %tmp1, 1112 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5113 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2114 %tmp8 = fdiv half %tmp7, 1.000000e+00115 store half %tmp8, ptr addrspace(1) %tmp6, align 2116 ret void117}118 119define void @frem_combine_v2f16(ptr addrspace(1) %arg) {120; GCN-LABEL: define void @frem_combine_v2f16(121; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {122; GCN-NEXT: [[BB:.*:]]123; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()124; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64125; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]126; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2127; GCN-NEXT: [[TMP1:%.*]] = frem <2 x half> [[TMP0]], splat (half 0xH3C00)128; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2129; GCN-NEXT: ret void130;131bb:132 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()133 %tmp1 = zext i32 %tmp to i64134 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1135 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2136 %tmp4 = frem half %tmp3, 1.000000e+00137 store half %tmp4, ptr addrspace(1) %tmp2, align 2138 %tmp5 = add nuw nsw i64 %tmp1, 1139 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5140 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2141 %tmp8 = frem half %tmp7, 1.000000e+00142 store half %tmp8, ptr addrspace(1) %tmp6, align 2143 ret void144}145 146; FIXME: Should not vectorize on gfx8147define amdgpu_kernel void @fma_combine_v2f16(ptr addrspace(1) %arg) {148; GCN-LABEL: define amdgpu_kernel void @fma_combine_v2f16(149; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {150; GCN-NEXT: [[BB:.*:]]151; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()152; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64153; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]154; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2155; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00), <2 x half> splat (half 0xH3C00))156; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2157; GCN-NEXT: ret void158;159bb:160 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()161 %tmp1 = zext i32 %tmp to i64162 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1163 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2164 %tmp4 = tail call half @llvm.fma.f16(half %tmp3, half 1.000000e+00, half 1.000000e+00)165 store half %tmp4, ptr addrspace(1) %tmp2, align 2166 %tmp5 = add nuw nsw i64 %tmp1, 1167 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5168 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2169 %tmp8 = tail call half @llvm.fma.f16(half %tmp7, half 1.000000e+00, half 1.000000e+00)170 store half %tmp8, ptr addrspace(1) %tmp6, align 2171 ret void172}173 174; FIXME: Should not vectorize on gfx8175define amdgpu_kernel void @fmuladd_combine_v2f16(ptr addrspace(1) %arg) {176; GCN-LABEL: define amdgpu_kernel void @fmuladd_combine_v2f16(177; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {178; GCN-NEXT: [[BB:.*:]]179; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()180; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64181; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]182; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2183; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00), <2 x half> splat (half 0xH3C00))184; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2185; GCN-NEXT: ret void186;187bb:188 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()189 %tmp1 = zext i32 %tmp to i64190 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1191 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2192 %tmp4 = tail call half @llvm.fmuladd.f16(half %tmp3, half 1.000000e+00, half 1.000000e+00)193 store half %tmp4, ptr addrspace(1) %tmp2, align 2194 %tmp5 = add nuw nsw i64 %tmp1, 1195 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5196 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2197 %tmp8 = tail call half @llvm.fmuladd.f16(half %tmp7, half 1.000000e+00, half 1.000000e+00)198 store half %tmp8, ptr addrspace(1) %tmp6, align 2199 ret void200}201 202 203define void @minnum_combine_v2f16(ptr addrspace(1) %arg) {204; GFX8-LABEL: define void @minnum_combine_v2f16(205; GFX8-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {206; GFX8-NEXT: [[BB:.*:]]207; GFX8-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()208; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64209; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]210; GFX8-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2211; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.minnum.f16(half [[ITMP3]], half 0xH3C00)212; GFX8-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2213; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1214; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]215; GFX8-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2216; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.minnum.f16(half [[ITMP7]], half 0xH3C00)217; GFX8-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2218; GFX8-NEXT: ret void219;220; GFX9-LABEL: define void @minnum_combine_v2f16(221; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {222; GFX9-NEXT: [[BB:.*:]]223; GFX9-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()224; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64225; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]226; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2227; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))228; GFX9-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2229; GFX9-NEXT: ret void230;231bb:232 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()233 %tmp1 = zext i32 %tmp to i64234 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1235 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2236 %tmp4 = call half @llvm.minnum.f16(half %tmp3, half 1.000000e+00)237 store half %tmp4, ptr addrspace(1) %tmp2, align 2238 %tmp5 = add nuw nsw i64 %tmp1, 1239 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5240 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2241 %tmp8 = call half @llvm.minnum.f16(half %tmp7, half 1.000000e+00)242 store half %tmp8, ptr addrspace(1) %tmp6, align 2243 ret void244}245 246 247define void @maxnum_combine_v2f16(ptr addrspace(1) %arg) {248; GFX8-LABEL: define void @maxnum_combine_v2f16(249; GFX8-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {250; GFX8-NEXT: [[BB:.*:]]251; GFX8-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()252; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64253; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]254; GFX8-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2255; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.maxnum.f16(half [[ITMP3]], half 0xH3C00)256; GFX8-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2257; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1258; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]259; GFX8-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2260; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.maxnum.f16(half [[ITMP7]], half 0xH3C00)261; GFX8-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2262; GFX8-NEXT: ret void263;264; GFX9-LABEL: define void @maxnum_combine_v2f16(265; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {266; GFX9-NEXT: [[BB:.*:]]267; GFX9-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()268; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64269; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]270; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2271; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maxnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))272; GFX9-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2273; GFX9-NEXT: ret void274;275bb:276 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()277 %tmp1 = zext i32 %tmp to i64278 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1279 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2280 %tmp4 = call half @llvm.maxnum.f16(half %tmp3, half 1.000000e+00)281 store half %tmp4, ptr addrspace(1) %tmp2, align 2282 %tmp5 = add nuw nsw i64 %tmp1, 1283 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5284 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2285 %tmp8 = call half @llvm.maxnum.f16(half %tmp7, half 1.000000e+00)286 store half %tmp8, ptr addrspace(1) %tmp6, align 2287 ret void288}289 290; FIXME: Should vectorize291define void @minimum_combine_v2f16(ptr addrspace(1) %arg) {292; GCN-LABEL: define void @minimum_combine_v2f16(293; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {294; GCN-NEXT: [[BB:.*:]]295; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()296; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64297; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]298; GCN-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2299; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.minimum.f16(half [[ITMP3]], half 0xH3C00)300; GCN-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2301; GCN-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1302; GCN-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]303; GCN-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2304; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.minimum.f16(half [[ITMP7]], half 0xH3C00)305; GCN-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2306; GCN-NEXT: ret void307;308bb:309 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()310 %tmp1 = zext i32 %tmp to i64311 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1312 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2313 %tmp4 = call half @llvm.minimum.f16(half %tmp3, half 1.000000e+00)314 store half %tmp4, ptr addrspace(1) %tmp2, align 2315 %tmp5 = add nuw nsw i64 %tmp1, 1316 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5317 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2318 %tmp8 = call half @llvm.minimum.f16(half %tmp7, half 1.000000e+00)319 store half %tmp8, ptr addrspace(1) %tmp6, align 2320 ret void321}322 323define void @maximum_combine_v2f16(ptr addrspace(1) %arg) {324; GCN-LABEL: define void @maximum_combine_v2f16(325; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {326; GCN-NEXT: [[BB:.*:]]327; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()328; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64329; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]330; GCN-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2331; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.maximum.f16(half [[ITMP3]], half 0xH3C00)332; GCN-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2333; GCN-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1334; GCN-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]335; GCN-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2336; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.maximum.f16(half [[ITMP7]], half 0xH3C00)337; GCN-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2338; GCN-NEXT: ret void339;340bb:341 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()342 %tmp1 = zext i32 %tmp to i64343 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1344 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2345 %tmp4 = call half @llvm.maximum.f16(half %tmp3, half 1.000000e+00)346 store half %tmp4, ptr addrspace(1) %tmp2, align 2347 %tmp5 = add nuw nsw i64 %tmp1, 1348 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5349 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2350 %tmp8 = call half @llvm.maximum.f16(half %tmp7, half 1.000000e+00)351 store half %tmp8, ptr addrspace(1) %tmp6, align 2352 ret void353}354 355define void @canonicalize_combine_v2f16(ptr addrspace(1) %arg) {356; GCN-LABEL: define void @canonicalize_combine_v2f16(357; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {358; GCN-NEXT: [[BB:.*:]]359; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()360; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64361; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]362; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2363; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP0]])364; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2365; GCN-NEXT: ret void366;367bb:368 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()369 %tmp1 = zext i32 %tmp to i64370 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1371 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2372 %tmp4 = call half @llvm.canonicalize.f16(half %tmp3)373 store half %tmp4, ptr addrspace(1) %tmp2, align 2374 %tmp5 = add nuw nsw i64 %tmp1, 1375 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5376 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2377 %tmp8 = call half @llvm.canonicalize.f16(half %tmp7)378 store half %tmp8, ptr addrspace(1) %tmp6, align 2379 ret void380}381 382define void @fabs_combine_v2f16(ptr addrspace(1) %arg) {383; GCN-LABEL: define void @fabs_combine_v2f16(384; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {385; GCN-NEXT: [[BB:.*:]]386; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()387; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64388; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]389; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2390; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[TMP0]])391; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2392; GCN-NEXT: ret void393;394bb:395 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()396 %tmp1 = zext i32 %tmp to i64397 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1398 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2399 %tmp4 = call half @llvm.fabs.f16(half %tmp3)400 store half %tmp4, ptr addrspace(1) %tmp2, align 2401 %tmp5 = add nuw nsw i64 %tmp1, 1402 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5403 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2404 %tmp8 = call half @llvm.fabs.f16(half %tmp7)405 store half %tmp8, ptr addrspace(1) %tmp6, align 2406 ret void407}408 409define void @fneg_combine_v2f16(ptr addrspace(1) %arg) {410; GCN-LABEL: define void @fneg_combine_v2f16(411; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {412; GCN-NEXT: [[BB:.*:]]413; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()414; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64415; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]416; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2417; GCN-NEXT: [[TMP1:%.*]] = fneg <2 x half> [[TMP0]]418; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2419; GCN-NEXT: ret void420;421bb:422 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()423 %tmp1 = zext i32 %tmp to i64424 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1425 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2426 %tmp4 = fneg half %tmp3427 store half %tmp4, ptr addrspace(1) %tmp2, align 2428 %tmp5 = add nuw nsw i64 %tmp1, 1429 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5430 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2431 %tmp8 = fneg half %tmp7432 store half %tmp8, ptr addrspace(1) %tmp6, align 2433 ret void434}435 436define void @copysign_combine_v2f16(ptr addrspace(1) %arg, half %sign) {437; GCN-LABEL: define void @copysign_combine_v2f16(438; GCN-SAME: ptr addrspace(1) [[ARG:%.*]], half [[SIGN:%.*]]) #[[ATTR0]] {439; GCN-NEXT: [[BB:.*:]]440; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()441; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64442; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]443; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2444; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i32 0445; GCN-NEXT: [[TMP2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <2 x i32> zeroinitializer446; GCN-NEXT: [[TMP3:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP0]], <2 x half> [[TMP2]])447; GCN-NEXT: store <2 x half> [[TMP3]], ptr addrspace(1) [[ITMP2]], align 2448; GCN-NEXT: ret void449;450bb:451 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()452 %tmp1 = zext i32 %tmp to i64453 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1454 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2455 %tmp4 = call half @llvm.copysign.f16(half %tmp3, half %sign)456 store half %tmp4, ptr addrspace(1) %tmp2, align 2457 %tmp5 = add nuw nsw i64 %tmp1, 1458 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5459 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2460 %tmp8 = call half @llvm.copysign.f16(half %tmp7, half %sign)461 store half %tmp8, ptr addrspace(1) %tmp6, align 2462 ret void463}464 465; FIXME: Should always vectorize466 467define void @copysign_combine_v4f16(ptr addrspace(1) %arg, half %sign) {468; GFX8-LABEL: define void @copysign_combine_v4f16(469; GFX8-SAME: ptr addrspace(1) [[ARG:%.*]], half [[SIGN:%.*]]) #[[ATTR0]] {470; GFX8-NEXT: [[BB:.*:]]471; GFX8-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()472; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64473; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]474; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1475; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]476; GFX8-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2477; GFX8-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i32 0478; GFX8-NEXT: [[TMP2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <2 x i32> zeroinitializer479; GFX8-NEXT: [[TMP3:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP0]], <2 x half> [[TMP2]])480; GFX8-NEXT: store <2 x half> [[TMP3]], ptr addrspace(1) [[ITMP2]], align 2481; GFX8-NEXT: [[ITMP9:%.*]] = add nuw nsw i64 [[ITMP1]], 2482; GFX8-NEXT: [[ITMP10:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP9]]483; GFX8-NEXT: [[ITMP11:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2484; GFX8-NEXT: [[ITMP12:%.*]] = call half @llvm.copysign.f16(half [[ITMP11]], half [[SIGN]])485; GFX8-NEXT: store half [[ITMP12]], ptr addrspace(1) [[ITMP10]], align 2486; GFX8-NEXT: [[ITMP13:%.*]] = add nuw nsw i64 [[ITMP1]], 3487; GFX8-NEXT: [[ITMP14:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP13]]488; GFX8-NEXT: [[ITMP15:%.*]] = load half, ptr addrspace(1) [[ITMP14]], align 2489; GFX8-NEXT: [[ITMP16:%.*]] = call half @llvm.copysign.f16(half [[ITMP15]], half [[SIGN]])490; GFX8-NEXT: store half [[ITMP16]], ptr addrspace(1) [[ITMP14]], align 2491; GFX8-NEXT: ret void492;493; GFX9-LABEL: define void @copysign_combine_v4f16(494; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]], half [[SIGN:%.*]]) #[[ATTR0]] {495; GFX9-NEXT: [[BB:.*:]]496; GFX9-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()497; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64498; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]499; GFX9-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1500; GFX9-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]501; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2502; GFX9-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i32 0503; GFX9-NEXT: [[TMP2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <2 x i32> zeroinitializer504; GFX9-NEXT: [[TMP3:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP0]], <2 x half> [[TMP2]])505; GFX9-NEXT: store <2 x half> [[TMP3]], ptr addrspace(1) [[ITMP2]], align 2506; GFX9-NEXT: [[ITMP9:%.*]] = add nuw nsw i64 [[ITMP1]], 2507; GFX9-NEXT: [[ITMP10:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP9]]508; GFX9-NEXT: [[ITMP11:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2509; GFX9-NEXT: [[ITMP13:%.*]] = add nuw nsw i64 [[ITMP1]], 3510; GFX9-NEXT: [[ITMP14:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP13]]511; GFX9-NEXT: [[ITMP15:%.*]] = load half, ptr addrspace(1) [[ITMP14]], align 2512; GFX9-NEXT: [[TMP4:%.*]] = insertelement <2 x half> poison, half [[ITMP11]], i32 0513; GFX9-NEXT: [[TMP5:%.*]] = insertelement <2 x half> [[TMP4]], half [[ITMP15]], i32 1514; GFX9-NEXT: [[TMP6:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP5]], <2 x half> [[TMP2]])515; GFX9-NEXT: store <2 x half> [[TMP6]], ptr addrspace(1) [[ITMP10]], align 2516; GFX9-NEXT: ret void517;518bb:519 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()520 %tmp1 = zext i32 %tmp to i64521 522 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1523 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2524 %tmp4 = call half @llvm.copysign.f16(half %tmp3, half %sign)525 store half %tmp4, ptr addrspace(1) %tmp2, align 2526 527 %tmp5 = add nuw nsw i64 %tmp1, 1528 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5529 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2530 %tmp8 = call half @llvm.copysign.f16(half %tmp7, half %sign)531 store half %tmp8, ptr addrspace(1) %tmp6, align 2532 533 %tmp9 = add nuw nsw i64 %tmp1, 2534 %tmp10 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp9535 %tmp11 = load half, ptr addrspace(1) %tmp6, align 2536 %tmp12 = call half @llvm.copysign.f16(half %tmp11, half %sign)537 store half %tmp12, ptr addrspace(1) %tmp10, align 2538 539 %tmp13 = add nuw nsw i64 %tmp1, 3540 %tmp14 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp13541 %tmp15 = load half, ptr addrspace(1) %tmp14, align 2542 %tmp16 = call half @llvm.copysign.f16(half %tmp15, half %sign)543 store half %tmp16, ptr addrspace(1) %tmp14, align 2544 ret void545}546 547 548define void @canonicalize_combine_v4f16(ptr addrspace(1) %arg) {549; GFX8-LABEL: define void @canonicalize_combine_v4f16(550; GFX8-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {551; GFX8-NEXT: [[BB:.*:]]552; GFX8-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()553; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64554; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]555; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1556; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]557; GFX8-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2558; GFX8-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP0]])559; GFX8-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2560; GFX8-NEXT: [[ITMP9:%.*]] = add nuw nsw i64 [[ITMP1]], 2561; GFX8-NEXT: [[ITMP10:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP9]]562; GFX8-NEXT: [[ITMP11:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2563; GFX8-NEXT: [[ITMP12:%.*]] = call half @llvm.canonicalize.f16(half [[ITMP11]])564; GFX8-NEXT: store half [[ITMP12]], ptr addrspace(1) [[ITMP10]], align 2565; GFX8-NEXT: [[ITMP13:%.*]] = add nuw nsw i64 [[ITMP1]], 3566; GFX8-NEXT: [[ITMP14:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP13]]567; GFX8-NEXT: [[ITMP15:%.*]] = load half, ptr addrspace(1) [[ITMP14]], align 2568; GFX8-NEXT: [[ITMP16:%.*]] = call half @llvm.canonicalize.f16(half [[ITMP15]])569; GFX8-NEXT: store half [[ITMP16]], ptr addrspace(1) [[ITMP14]], align 2570; GFX8-NEXT: ret void571;572; GFX9-LABEL: define void @canonicalize_combine_v4f16(573; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {574; GFX9-NEXT: [[BB:.*:]]575; GFX9-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()576; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64577; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]578; GFX9-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1579; GFX9-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]580; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2581; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP0]])582; GFX9-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2583; GFX9-NEXT: [[ITMP9:%.*]] = add nuw nsw i64 [[ITMP1]], 2584; GFX9-NEXT: [[ITMP10:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP9]]585; GFX9-NEXT: [[ITMP11:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2586; GFX9-NEXT: [[ITMP13:%.*]] = add nuw nsw i64 [[ITMP1]], 3587; GFX9-NEXT: [[ITMP14:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP13]]588; GFX9-NEXT: [[ITMP15:%.*]] = load half, ptr addrspace(1) [[ITMP14]], align 2589; GFX9-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[ITMP11]], i32 0590; GFX9-NEXT: [[TMP3:%.*]] = insertelement <2 x half> [[TMP2]], half [[ITMP15]], i32 1591; GFX9-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP3]])592; GFX9-NEXT: store <2 x half> [[TMP4]], ptr addrspace(1) [[ITMP10]], align 2593; GFX9-NEXT: ret void594;595bb:596 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()597 %tmp1 = zext i32 %tmp to i64598 599 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1600 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2601 %tmp4 = call half @llvm.canonicalize.f16(half %tmp3)602 store half %tmp4, ptr addrspace(1) %tmp2, align 2603 604 %tmp5 = add nuw nsw i64 %tmp1, 1605 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5606 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2607 %tmp8 = call half @llvm.canonicalize.f16(half %tmp7)608 store half %tmp8, ptr addrspace(1) %tmp6, align 2609 610 %tmp9 = add nuw nsw i64 %tmp1, 2611 %tmp10 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp9612 %tmp11 = load half, ptr addrspace(1) %tmp6, align 2613 %tmp12 = call half @llvm.canonicalize.f16(half %tmp11)614 store half %tmp12, ptr addrspace(1) %tmp10, align 2615 616 %tmp13 = add nuw nsw i64 %tmp1, 3617 %tmp14 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp13618 %tmp15 = load half, ptr addrspace(1) %tmp14, align 2619 %tmp16 = call half @llvm.canonicalize.f16(half %tmp15)620 store half %tmp16, ptr addrspace(1) %tmp14, align 2621 ret void622}623 624; FIXME: Should not vectorize on gfx8625define void @minimumnum_combine_v2f16(ptr addrspace(1) %arg) {626; GCN-LABEL: define void @minimumnum_combine_v2f16(627; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {628; GCN-NEXT: [[BB:.*:]]629; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()630; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64631; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]632; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2633; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))634; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2635; GCN-NEXT: ret void636;637bb:638 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()639 %tmp1 = zext i32 %tmp to i64640 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1641 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2642 %tmp4 = call half @llvm.minimumnum.f16(half %tmp3, half 1.000000e+00)643 store half %tmp4, ptr addrspace(1) %tmp2, align 2644 %tmp5 = add nuw nsw i64 %tmp1, 1645 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5646 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2647 %tmp8 = call half @llvm.minimumnum.f16(half %tmp7, half 1.000000e+00)648 store half %tmp8, ptr addrspace(1) %tmp6, align 2649 ret void650}651 652; FIXME: Should not vectorize on gfx8653define void @maximumnum_combine_v2f16(ptr addrspace(1) %arg) {654; GCN-LABEL: define void @maximumnum_combine_v2f16(655; GCN-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {656; GCN-NEXT: [[BB:.*:]]657; GCN-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()658; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64659; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]660; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2661; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))662; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2663; GCN-NEXT: ret void664;665bb:666 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()667 %tmp1 = zext i32 %tmp to i64668 %tmp2 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp1669 %tmp3 = load half, ptr addrspace(1) %tmp2, align 2670 %tmp4 = call half @llvm.maximumnum.f16(half %tmp3, half 1.000000e+00)671 store half %tmp4, ptr addrspace(1) %tmp2, align 2672 %tmp5 = add nuw nsw i64 %tmp1, 1673 %tmp6 = getelementptr inbounds half, ptr addrspace(1) %arg, i64 %tmp5674 %tmp7 = load half, ptr addrspace(1) %tmp6, align 2675 %tmp8 = call half @llvm.maximumnum.f16(half %tmp7, half 1.000000e+00)676 store half %tmp8, ptr addrspace(1) %tmp6, align 2677 ret void678}679