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1; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX908 %s2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX90A %s3 4; GCN-LABEL: @fadd_combine5; GFX908: fadd float6; GFX908: fadd float7; GFX90A: fadd <2 x float>8define amdgpu_kernel void @fadd_combine(ptr addrspace(1) %arg) {9bb:10 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()11 %tmp1 = zext i32 %tmp to i6412 %tmp2 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp113 %tmp3 = load float, ptr addrspace(1) %tmp2, align 414 %tmp4 = fadd float %tmp3, 1.000000e+0015 store float %tmp4, ptr addrspace(1) %tmp2, align 416 %tmp5 = add nuw nsw i64 %tmp1, 117 %tmp6 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp518 %tmp7 = load float, ptr addrspace(1) %tmp6, align 419 %tmp8 = fadd float %tmp7, 1.000000e+0020 store float %tmp8, ptr addrspace(1) %tmp6, align 421 ret void22}23 24; GCN-LABEL: @fmul_combine25; GFX908: fmul float26; GFX908: fmul float27; GFX90A: fmul <2 x float>28define amdgpu_kernel void @fmul_combine(ptr addrspace(1) %arg) {29bb:30 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()31 %tmp1 = zext i32 %tmp to i6432 %tmp2 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp133 %tmp3 = load float, ptr addrspace(1) %tmp2, align 434 %tmp4 = fmul float %tmp3, 1.000000e+0035 store float %tmp4, ptr addrspace(1) %tmp2, align 436 %tmp5 = add nuw nsw i64 %tmp1, 137 %tmp6 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp538 %tmp7 = load float, ptr addrspace(1) %tmp6, align 439 %tmp8 = fmul float %tmp7, 1.000000e+0040 store float %tmp8, ptr addrspace(1) %tmp6, align 441 ret void42}43 44; GCN-LABEL: @fma_combine45; GFX908: call float @llvm.fma.f3246; GFX908: call float @llvm.fma.f3247; GFX90A: call <2 x float> @llvm.fma.v2f3248define amdgpu_kernel void @fma_combine(ptr addrspace(1) %arg) {49bb:50 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()51 %tmp1 = zext i32 %tmp to i6452 %tmp2 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp153 %tmp3 = load float, ptr addrspace(1) %tmp2, align 454 %tmp4 = tail call float @llvm.fma.f32(float %tmp3, float 1.000000e+00, float 1.000000e+00)55 store float %tmp4, ptr addrspace(1) %tmp2, align 456 %tmp5 = add nuw nsw i64 %tmp1, 157 %tmp6 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp558 %tmp7 = load float, ptr addrspace(1) %tmp6, align 459 %tmp8 = tail call float @llvm.fma.f32(float %tmp7, float 1.000000e+00, float 1.000000e+00)60 store float %tmp8, ptr addrspace(1) %tmp6, align 461 ret void62}63 64declare i32 @llvm.amdgcn.workitem.id.x()65declare float @llvm.fma.f32(float, float, float)66 67