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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mcpu=swift -mtriple=thumbv7-apple-ios -passes=slp-vectorizer < %s | FileCheck %s3 4target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"5 6%class.Complex = type { double, double }7 8; Code like this is the result of SROA. Make sure we don't vectorize this9; because the scalar version of the shl/or are handled by the10; backend and disappear, the vectorized code stays.11 12define void @SROAed(ptr noalias nocapture sret(%class.Complex) %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) {13; CHECK-LABEL: @SROAed(14; CHECK-NEXT: entry:15; CHECK-NEXT: [[A_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i32] [[A_COERCE:%.*]], 016; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[A_COERCE_FCA_0_EXTRACT]] to i6417; CHECK-NEXT: [[A_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i32] [[A_COERCE]], 118; CHECK-NEXT: [[A_SROA_0_4_INSERT_EXT:%.*]] = zext i32 [[A_COERCE_FCA_1_EXTRACT]] to i6419; CHECK-NEXT: [[A_SROA_0_4_INSERT_SHIFT:%.*]] = shl nuw i64 [[A_SROA_0_4_INSERT_EXT]], 3220; CHECK-NEXT: [[A_SROA_0_4_INSERT_INSERT:%.*]] = or i64 [[A_SROA_0_4_INSERT_SHIFT]], [[A_SROA_0_0_INSERT_EXT]]21; CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_SROA_0_4_INSERT_INSERT]] to double22; CHECK-NEXT: [[A_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i32] [[A_COERCE]], 223; CHECK-NEXT: [[A_SROA_3_8_INSERT_EXT:%.*]] = zext i32 [[A_COERCE_FCA_2_EXTRACT]] to i6424; CHECK-NEXT: [[A_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i32] [[A_COERCE]], 325; CHECK-NEXT: [[A_SROA_3_12_INSERT_EXT:%.*]] = zext i32 [[A_COERCE_FCA_3_EXTRACT]] to i6426; CHECK-NEXT: [[A_SROA_3_12_INSERT_SHIFT:%.*]] = shl nuw i64 [[A_SROA_3_12_INSERT_EXT]], 3227; CHECK-NEXT: [[A_SROA_3_12_INSERT_INSERT:%.*]] = or i64 [[A_SROA_3_12_INSERT_SHIFT]], [[A_SROA_3_8_INSERT_EXT]]28; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_SROA_3_12_INSERT_INSERT]] to double29; CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i32] [[B_COERCE:%.*]], 030; CHECK-NEXT: [[B_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[B_COERCE_FCA_0_EXTRACT]] to i6431; CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i32] [[B_COERCE]], 132; CHECK-NEXT: [[B_SROA_0_4_INSERT_EXT:%.*]] = zext i32 [[B_COERCE_FCA_1_EXTRACT]] to i6433; CHECK-NEXT: [[B_SROA_0_4_INSERT_SHIFT:%.*]] = shl nuw i64 [[B_SROA_0_4_INSERT_EXT]], 3234; CHECK-NEXT: [[B_SROA_0_4_INSERT_INSERT:%.*]] = or i64 [[B_SROA_0_4_INSERT_SHIFT]], [[B_SROA_0_0_INSERT_EXT]]35; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_SROA_0_4_INSERT_INSERT]] to double36; CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i32] [[B_COERCE]], 237; CHECK-NEXT: [[B_SROA_3_8_INSERT_EXT:%.*]] = zext i32 [[B_COERCE_FCA_2_EXTRACT]] to i6438; CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i32] [[B_COERCE]], 339; CHECK-NEXT: [[B_SROA_3_12_INSERT_EXT:%.*]] = zext i32 [[B_COERCE_FCA_3_EXTRACT]] to i6440; CHECK-NEXT: [[B_SROA_3_12_INSERT_SHIFT:%.*]] = shl nuw i64 [[B_SROA_3_12_INSERT_EXT]], 3241; CHECK-NEXT: [[B_SROA_3_12_INSERT_INSERT:%.*]] = or i64 [[B_SROA_3_12_INSERT_SHIFT]], [[B_SROA_3_8_INSERT_EXT]]42; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_SROA_3_12_INSERT_INSERT]] to double43; CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP0]], [[TMP2]]44; CHECK-NEXT: [[ADD3:%.*]] = fadd double [[TMP1]], [[TMP3]]45; CHECK-NEXT: store double [[ADD]], ptr [[AGG_RESULT:%.*]], align 446; CHECK-NEXT: [[IM_I_I:%.*]] = getelementptr inbounds [[CLASS_COMPLEX:%.*]], ptr [[AGG_RESULT]], i32 0, i32 147; CHECK-NEXT: store double [[ADD3]], ptr [[IM_I_I]], align 448; CHECK-NEXT: ret void49;50entry:51 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 052 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i6453 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 154 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i6455 %a.sroa.0.4.insert.shift = shl nuw i64 %a.sroa.0.4.insert.ext, 3256 %a.sroa.0.4.insert.insert = or i64 %a.sroa.0.4.insert.shift, %a.sroa.0.0.insert.ext57 %0 = bitcast i64 %a.sroa.0.4.insert.insert to double58 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce, 259 %a.sroa.3.8.insert.ext = zext i32 %a.coerce.fca.2.extract to i6460 %a.coerce.fca.3.extract = extractvalue [4 x i32] %a.coerce, 361 %a.sroa.3.12.insert.ext = zext i32 %a.coerce.fca.3.extract to i6462 %a.sroa.3.12.insert.shift = shl nuw i64 %a.sroa.3.12.insert.ext, 3263 %a.sroa.3.12.insert.insert = or i64 %a.sroa.3.12.insert.shift, %a.sroa.3.8.insert.ext64 %1 = bitcast i64 %a.sroa.3.12.insert.insert to double65 %b.coerce.fca.0.extract = extractvalue [4 x i32] %b.coerce, 066 %b.sroa.0.0.insert.ext = zext i32 %b.coerce.fca.0.extract to i6467 %b.coerce.fca.1.extract = extractvalue [4 x i32] %b.coerce, 168 %b.sroa.0.4.insert.ext = zext i32 %b.coerce.fca.1.extract to i6469 %b.sroa.0.4.insert.shift = shl nuw i64 %b.sroa.0.4.insert.ext, 3270 %b.sroa.0.4.insert.insert = or i64 %b.sroa.0.4.insert.shift, %b.sroa.0.0.insert.ext71 %2 = bitcast i64 %b.sroa.0.4.insert.insert to double72 %b.coerce.fca.2.extract = extractvalue [4 x i32] %b.coerce, 273 %b.sroa.3.8.insert.ext = zext i32 %b.coerce.fca.2.extract to i6474 %b.coerce.fca.3.extract = extractvalue [4 x i32] %b.coerce, 375 %b.sroa.3.12.insert.ext = zext i32 %b.coerce.fca.3.extract to i6476 %b.sroa.3.12.insert.shift = shl nuw i64 %b.sroa.3.12.insert.ext, 3277 %b.sroa.3.12.insert.insert = or i64 %b.sroa.3.12.insert.shift, %b.sroa.3.8.insert.ext78 %3 = bitcast i64 %b.sroa.3.12.insert.insert to double79 %add = fadd double %0, %280 %add3 = fadd double %1, %381 store double %add, ptr %agg.result, align 482 %im.i.i = getelementptr inbounds %class.Complex, ptr %agg.result, i32 0, i32 183 store double %add3, ptr %im.i.i, align 484 ret void85}86