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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 | FileCheck %s -check-prefix=VECTOR3; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_80 | FileCheck %s -check-prefix=VECTOR4; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_70 | FileCheck %s -check-prefix=VECTOR5; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_50 | FileCheck %s -check-prefix=NOVECTOR6 7define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %arg, ptr noalias nocapture readonly align 256 dereferenceable(19267584) %arg1, i32 %arg2, i32 %arg3) local_unnamed_addr #0 {8; VECTOR-LABEL: @fusion(9; VECTOR-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[ARG2:%.*]], 610; VECTOR-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG3:%.*]]11; VECTOR-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP2]], 212; VECTOR-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i6413; VECTOR-NEXT: [[TMP5:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP4]]14; VECTOR-NEXT: [[TMP6:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP4]]15; VECTOR-NEXT: [[TMP7:%.*]] = load <2 x half>, ptr [[TMP5]], align 816; VECTOR-NEXT: [[TMP8:%.*]] = fmul fast <2 x half> [[TMP7]], splat (half 0xH5380)17; VECTOR-NEXT: [[TMP9:%.*]] = fadd fast <2 x half> [[TMP8]], splat (half 0xH57F0)18; VECTOR-NEXT: store <2 x half> [[TMP9]], ptr [[TMP6]], align 819; VECTOR-NEXT: ret void20;21; NOVECTOR-LABEL: @fusion(22; NOVECTOR-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[ARG2:%.*]], 623; NOVECTOR-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG3:%.*]]24; NOVECTOR-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP2]], 225; NOVECTOR-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i6426; NOVECTOR-NEXT: [[TMP10:%.*]] = or disjoint i64 [[TMP4]], 127; NOVECTOR-NEXT: [[TMP5:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP4]]28; NOVECTOR-NEXT: [[TMP7:%.*]] = load half, ptr [[TMP5]], align 829; NOVECTOR-NEXT: [[TMP8:%.*]] = fmul fast half [[TMP7]], 0xH538030; NOVECTOR-NEXT: [[TMP9:%.*]] = fadd fast half [[TMP8]], 0xH57F031; NOVECTOR-NEXT: [[TMP6:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP4]]32; NOVECTOR-NEXT: store half [[TMP9]], ptr [[TMP6]], align 833; NOVECTOR-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1]], i64 [[TMP10]]34; NOVECTOR-NEXT: [[TMP12:%.*]] = load half, ptr [[TMP11]], align 235; NOVECTOR-NEXT: [[TMP13:%.*]] = fmul fast half [[TMP12]], 0xH538036; NOVECTOR-NEXT: [[TMP14:%.*]] = fadd fast half [[TMP13]], 0xH57F037; NOVECTOR-NEXT: [[TMP15:%.*]] = getelementptr inbounds half, ptr [[ARG]], i64 [[TMP10]]38; NOVECTOR-NEXT: store half [[TMP14]], ptr [[TMP15]], align 239; NOVECTOR-NEXT: ret void40;41 %1 = shl nuw nsw i32 %arg2, 642 %4 = or i32 %1, %arg343 %5 = shl nuw nsw i32 %4, 244 %6 = zext i32 %5 to i6445 %7 = or disjoint i64 %6, 146 %11 = getelementptr inbounds half, ptr %arg1, i64 %647 %12 = load half, ptr %11, align 848 %13 = fmul fast half %12, 0xH538049 %14 = fadd fast half %13, 0xH57F050 %16 = getelementptr inbounds half, ptr %arg, i64 %651 store half %14, ptr %16, align 852 %17 = getelementptr inbounds half, ptr %arg1, i64 %753 %18 = load half, ptr %17, align 254 %19 = fmul fast half %18, 0xH538055 %20 = fadd fast half %19, 0xH57F056 %21 = getelementptr inbounds half, ptr %arg, i64 %757 store half %20, ptr %21, align 258 ret void59}60 61define ptx_kernel void @add_f16(ptr addrspace(1) %0, { half, half } %1, { half, half } %2) {62; VECTOR-LABEL: @add_f16(63; VECTOR-NEXT: [[TMP4:%.*]] = extractvalue { half, half } [[TMP1:%.*]], 064; VECTOR-NEXT: [[TMP5:%.*]] = extractvalue { half, half } [[TMP1]], 165; VECTOR-NEXT: [[TMP6:%.*]] = extractvalue { half, half } [[TMP2:%.*]], 066; VECTOR-NEXT: [[TMP7:%.*]] = extractvalue { half, half } [[TMP2]], 167; VECTOR-NEXT: [[TMP8:%.*]] = insertelement <2 x half> poison, half [[TMP4]], i32 068; VECTOR-NEXT: [[TMP9:%.*]] = insertelement <2 x half> [[TMP8]], half [[TMP5]], i32 169; VECTOR-NEXT: [[TMP10:%.*]] = insertelement <2 x half> poison, half [[TMP6]], i32 070; VECTOR-NEXT: [[TMP11:%.*]] = insertelement <2 x half> [[TMP10]], half [[TMP7]], i32 171; VECTOR-NEXT: [[TMP12:%.*]] = fadd <2 x half> [[TMP9]], [[TMP11]]72; VECTOR-NEXT: [[TMP13:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()73; VECTOR-NEXT: [[TMP14:%.*]] = shl i32 [[TMP13]], 174; VECTOR-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 6275; VECTOR-NEXT: [[TMP16:%.*]] = zext nneg i32 [[TMP15]] to i6476; VECTOR-NEXT: [[TMP17:%.*]] = getelementptr half, ptr addrspace(1) [[TMP0:%.*]], i64 [[TMP16]]77; VECTOR-NEXT: store <2 x half> [[TMP12]], ptr addrspace(1) [[TMP17]], align 478; VECTOR-NEXT: ret void79;80; NOVECTOR-LABEL: @add_f16(81; NOVECTOR-NEXT: [[TMP4:%.*]] = extractvalue { half, half } [[TMP1:%.*]], 082; NOVECTOR-NEXT: [[TMP5:%.*]] = extractvalue { half, half } [[TMP1]], 183; NOVECTOR-NEXT: [[TMP6:%.*]] = extractvalue { half, half } [[TMP2:%.*]], 084; NOVECTOR-NEXT: [[TMP7:%.*]] = extractvalue { half, half } [[TMP2]], 185; NOVECTOR-NEXT: [[TMP8:%.*]] = fadd half [[TMP4]], [[TMP6]]86; NOVECTOR-NEXT: [[TMP9:%.*]] = fadd half [[TMP5]], [[TMP7]]87; NOVECTOR-NEXT: [[TMP13:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()88; NOVECTOR-NEXT: [[TMP14:%.*]] = shl i32 [[TMP13]], 189; NOVECTOR-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 6290; NOVECTOR-NEXT: [[TMP16:%.*]] = zext nneg i32 [[TMP15]] to i6491; NOVECTOR-NEXT: [[TMP17:%.*]] = getelementptr half, ptr addrspace(1) [[TMP0:%.*]], i64 [[TMP16]]92; NOVECTOR-NEXT: [[TMP19:%.*]] = insertelement <2 x half> poison, half [[TMP8]], i64 093; NOVECTOR-NEXT: [[TMP12:%.*]] = insertelement <2 x half> [[TMP19]], half [[TMP9]], i64 194; NOVECTOR-NEXT: store <2 x half> [[TMP12]], ptr addrspace(1) [[TMP17]], align 495; NOVECTOR-NEXT: ret void96;97 %5 = extractvalue { half, half } %1, 098 %6 = extractvalue { half, half } %1, 199 %7 = extractvalue { half, half } %2, 0100 %8 = extractvalue { half, half } %2, 1101 %9 = fadd half %5, %7102 %10 = fadd half %6, %8103 %11 = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()104 %12 = shl i32 %11, 1105 %13 = and i32 %12, 62106 %14 = zext nneg i32 %13 to i64107 %15 = getelementptr half, ptr addrspace(1) %0, i64 %14108 %18 = insertelement <2 x half> poison, half %9, i64 0109 %19 = insertelement <2 x half> %18, half %10, i64 1110 store <2 x half> %19, ptr addrspace(1) %15, align 4111 ret void112}113 114; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)115declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1116 117attributes #0 = { nounwind }118attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }119